Skip to main content
SpringerLink
Log in

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya, and V. Verma, “Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault Tolerant Applications,” in IEEE Proc. of Int. Test Conf., 1999, pp. 973–982.

  2. M. Abramovici and C. Stroud, “BIST-Based Delay-Fault Testing in FPGAs,” in IEEE Proc. of Int. On-Line Testing Work., 2002, pp. 131–134.

  3. V. Betz, J. Rose, and A. Marquardt, Architecture Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999 (ISBN: 0-7923-8460-1).

  4. R.A. Carberry, S.P. Young, and T.J. Bauer, FPGA LookUp Table with High Speed Read Decoder, Xilinx Inc, San Jose, United States Patent No. 6621296 B2, 2003.

  5. E. Chmelar, “FPGA Interconnect Delay Fault Testing,” in IEEE Proc. of Int. Test Conf., 2003, pp. 1239–1247.

  6. P. Chow, S.O. Seo, J. Rose, K. Chung, G. Páez-Monzón and I. Rahardja, “The Design of an SRAM-based field-programmable Gate array, Part II: Circuit Design and Layout,” IEEE Trans. on VLSI Systems, vol. 7, no. 3, pp. 321–330, 1999.

    Article  Google Scholar 

  7. P. Girard, O. Héron, S. Pravossoudovitch, and M. Renovell, “Defect Analysis for Delay-Fault BIST in FPGAs,” in IEEE Proc. of Int. On-Line Testing Symp., 2003, pp. 124–128.

  8. P. Girard, O. Héron, S. Pravossoudovitch, and M. Renovell, “Requirements for Delay Testing of Look-Up Tables of SRAM-Based FPGAs,” in IEEE Proc of European Test Work., 2003, pp. 147–152.

  9. P. Girard, O. Héron, S. Pravossoudovitch, and M. Renovell, “High-Quality TPG for Delay Faults in Look-Up Tables of FPGAs,” in IEEE Work. on Electronic Design, Test and Applicat. (DELTA’04), Perth Western, Australia, 2004, pp. 83–88.

  10. I.G. Harris and R. Tessier, “Interconnect Testing in Cluster-Based FPGA Architectures,” in IEEE-SIGDA Design Automation Conference, 2000, pp. 49–54.

  11. I.G. Harris, P.R. Menon, and R. Tessier, “BIST-Based Delay Path Testing in FPGA Architectures,” in IEEE Proc. of Int. Test Conf., 2001, pp. 364–369.

  12. W.K. Huang, F.J. Meyer, X.T. Chen, and F. Lombardi, “Testing Configurable LUT-Based FPGAs,” IEEE Trans. On Very Large Scale Integration Systems, vol. 6, pp. 276–283, 1998.

    Article  Google Scholar 

  13. A. Krasniewski, “Application-Dependent Testing of FPGA Delay Faults,” in IEEE Proc. 25th Euromicro Conference-Informatics: Theory and Practice for the New Millennium (EUROMICRO’99), 1999, pp. 260–267.

  14. A. Krasniewski, “Exploiting Reconfigurability of Effective Detection of Delay Faults in LUT-Based FPGAs,” in IEEE Proc. of Int. Conf. on Field Programmable Logic & Applications, 2000, pp. 675–684.

  15. M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “SRAM-Based FPGAs: Testing the Embedded RAM Modules,” JETTA, Kluwer Academic Publisher, vol. 14, pp. 159–167, 1999.

  16. M. Renovell, J.M. Portal, P. Faure, J. Figueras, and Y. Zorian, “Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs,” in IEEE Proc. of European Test Work., 2000, pp. 157–162.

  17. M. Renovell and Y. Zorian, “Different Experiments in Test Generation for XILINX FPGAs,” in IEEE Proc. of Int. Test Conf., 2000, pp. 854–861.

  18. C. Stroud, S. Konola, P. Chen and M. Abramovici, “Built-In Self Test of Logic Blocks in FPGAs,” in IEEE Proc. of VLSI Test Symp., 1996, pp. 387–392.

  19. C. Stroud, E. Lee, and M. Abramovici, “Built-In Self Test of FPGA Interconnect,” in IEEE Proc. of Int. Test Conf., 1998, pp. 404–411.

  20. M. B. Tahoori, “Testing for Resistive Open Defects in FPGAs,” in IEEE Proc. of Int. Conf. on Field Programmable Technology, 2002, pp. 332–335.

  21. Xilinx Inc, Virtex Series Product Specification (FPGAs), San Jose, USA, v2.6, 2002.

  22. Xilinx Inc, FPGA Editor Tool, San Jose, USA, release v6.2i, 2004.

Download references

Author information

Authors and Affiliations

  1. Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France

    Patrick Girard, Olivier Héron, Serge Pravossoudovitch & Michel Renovell

Authors
  1. Patrick Girard
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Olivier Héron
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Serge Pravossoudovitch
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Michel Renovell
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Olivier Héron.

Additional information

Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Micro-electronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing, and low power testing. He has authored and co-authored more than 90 papers on these fields, and has supervised several PhD dissertations. He has also participated to several European research projects (Esprit III ATSEC, Eureka MEDEA, MEDEA+ ASSOCIATE, IST MARLOW). Patrick GIRARD holds a B.Sc. and a M.Sc. in Electrical Engineering, and obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992.

Olivier Héron is presently researcher at CEA (French Center for Technology Research) in the laboratory of Reliability for Embedded Systems. His research interests are Logic BIST, On-Line Testing, Delay Fault Testing of FPGAs and Fault Modelling. He is a member of the program commitee of the Field Programmable Logic Conference FPL2006. He received his Ph.D. from the University of Montpellier (France) in 2004 and worked in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He received the B.Sc. degree in 1998 and the M.Sc. degree in 2001 in Electrical Engineering from the University of Montpellier.

Serge Pravossoudovitch was born in 1957. He is currently Professor in the Electrical and Computer Engineering Department of the University of Montpellier and his research activities are performed at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He is received the Master degree in Electrical Engineering in 1979 from the University of Montpellier. He got his Ph.D. degree in Electrical Engineering in 1983 on symbolic layout for IC design. Since 1984, he was been interested in the testing domain. He obtained the “doctorat d’état” degree in 1987 for his works on switch level automatic test pattern generation. He is presently interested in delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, MEDEA).

Michel Renovell is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee) and Chair of the FPGA testing Committee. He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of several conferences: International Mixed Signal Testing Workshop IMSTW2000, Field Programmable Logic Conference FPL2002 and European Test Symposium ETS2004.

A preliminary version of this work has been presented at the 1st European Test Symposium 2004, in Ajaccio.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Girard, P., Héron, O., Pravossoudovitch, S. et al. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J Electron Test 22, 161–172 (2006). https://doi.org/10.1007/s10836-005-4631-1

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-005-4631-1

Keywords

Search

Navigation