Skip to main content
Log in

Error Diagnosis of Sequential Circuits Using Region-Based Model

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Algorithms to locate multiple design errors using region-based model are studied for both combinational and sequential circuits. The model takes locality aspect of errors and is based on a 3-value, non-enumerative analysis technique. Studies show the effectiveness of the region based model for single and multiple stuck faults and gate connection errors. For sequential circuits, we try to locate the time frame at which the error was first excited, by re-simulating as few vectors as possible preceding the erroneous vector in a fully initialized circuit to carry out the diagnosis. Experimental results on benchmark circuits are used to demonstrate rapid and accurate locating of multiple errors.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. M.S. Abadir, J. Ferguson, and T.E. Kirkland, “Login Design Verification via Test Generation,” in IEEE Transactions on Computer-Aided Design, vol. 7, no. 1, pp. 138–148, 1988.

    Google Scholar 

  2. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, New York, NY: Computer Science Press, 1990.

    Google Scholar 

  3. V. Boppana and M. Fujita, “Modeling the Unknown! to Wards Model-Independent Fault and Error Diagnosis,” in Proc. Intl. Test Conf., 1998, pp. 1094–1101.

  4. V. Boppana, R. Mukherjee, J. Jain, and M. Fujita, “Multiple Error Diagnosis Based on Xlists,” in Proc. Design Automation Conf., 1999, pp. 100–110.

  5. P.-Y. Chung, Y.-M. Wang, and I.N. Hajj, “Diagnosis and Correction of Logic Design Errors in Digital Circuits,” in Proc. Design Automation Conf., 1993, pp. 503–508.

  6. A.L. D’Souza and M.S. Hsiao, “Error Diagnosis of Sequential Circuits Using Region-Based Model,” in Proc. VLSI Design Conf., 2001, pp. 103–108.

  7. A.L. D’Souza and M.S. Hsiao, “On Quality of Test Sets: Relating Fault Coverage to Defect Coverage,” to appear in Proc. Annual Systems Readiness Technology Conf. (AUTOTESTCON), Aug. 2001.

  8. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” in Proc. IEEE Euro Design and Test Conf., 1997, pp. 22–28.

  9. S.-Y. Huang and K.-T Cheng, “ErrorTracer: Design Error Diagnosis Based on Fault Simulation Techniques,” in IEEE Trans. Computer-Aided Design, vol. 18, pp. 1341–1352, Sept. 1999.

    Google Scholar 

  10. A. Jain, V. Boppana, M.S. Hsiao, and M. Fujita, “On the Evaluation of Arbitrary Defect Coverage of Test Sets,” in Proc. VLSI Test Symp., 1999, pp. 426–432.

  11. A. Jain, V. Boppana, R. Mukherjee, J. Jain, M.S. Hsiao, and M. Fujita, “Testing, Verification, and Diagnosis in the Presence of Unknowns,” in Proc. IEEE VLSI Test Symp., 2000, pp. 263–269.

  12. D.B. Lavo, B. Chess, T. Larrabee, and I. Hartanto, “Probabilistic Mixed-Model Fault Diagnosis,” in Proc. Intl. Test Conf., 1998, pp. 1084–1093.

  13. H.-T. Liaw, J.-H. Tsaih, and C.-S. Lin, “Efficient Automatic Diagnosis of Digital Circuits,” in Proc. Intl. Conf. Computer-Aided Design, 1990, pp. 464–467.

  14. I. Pomeranz and S.M. Reddy, “On Diagnosis and Correction of Design Errors,” in Proc. Intl. Conf. Computer-Aided Design, 1993, pp. 500–507.

  15. I. Pomeranz and S.M. Reddy, “On Error Correction in Macro-Based Circuits,” in Proc. Intl. Conf. Computer-Aided Design, 1994, pp. 568–575.

  16. M. Tomita and H.-H. Jiang, “An Algorithm for Locating Logic Design Errors,” in Proc. Intl. Conf. Computer-Aided Design, 1990, pp. 468–471.

  17. M. Tomita, T. Yamamoto, F. Sumikawa, and K. Hirano, “Rectification of Multiple Logic Design Errors in Multiple Output Circuits,” in Proc. Design Automation Conf., 1994, pp. 212–217.

  18. D. Van Campenhout, H. Al-Asaad, J.P. Hayes, T. Mudge, and R. Brown, “High-Level Design Verification of Microprocessors via Error Modeling,” ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 4, pp. 581–599, 1998.

    Google Scholar 

  19. S. Venkataraman and S.B. Drummonds, “POIROT: A Logic Fault Diagnosis Tool and Its Applications,” in Proc. Intl. Test Conf., 2000, pp. 253–262.

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Anand L. D’Souza.

Additional information

This Research was Supported in Part by the New Jersey Commission on Science and Technology.

Anand D’Souza received his B.E. in electronics and communication engineering from Karnataka Regional Engineering College, India in 1998 and M.S. in electrical engineering from Rutgers University. Anand is currently pursuing his M.B.A. degree at the University of Chicago’s Graduate School of Business. Prior to joining the University of Chicago, he was working as a DFT engineer in the Processor and Network Products division of Sun Microsystems, Inc., California. His current interests include finance, strategic management and entrepreneurship.

Michael S. Hsiao received the B.S. in computer engineering with highest honors from the University of Illinois at Urbana-Champaign in 1992, and M.S. and Ph.D in electrical engineering in 1993 and 1997, respectively, from the same university. During his studies, he was recipient of the Digital Equipment Corporation Fellowship, McDonnell Douglas Scholarship, and Semiconductor Research Corp. Research Assistantship. Michael is currently an Associate Professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech in Blacksburg, Virginia. Prior to joining Virginia Tech in 2001, he was an Assistant Professor in the Department of Electrical and Computer Engineering at Rutgers University. In the summer of 1997, Michael was a visiting scientist at NEC USA in Princeton, NJ. During the summer of 2002, he was a visiting professor at Intel in Santa Clara, CA. Michael is a recipient of the National Science Foundation CAREER Award. He has published more than 100 refereed journal and conference papers in the areas of design, test, and verification of complex digital systems, as well as diagnosis and power management of these systems. He serves on the Editorial Board of the Journal of Electronic Testing: Theory and Applications.

Rights and permissions

Reprints and permissions

About this article

Cite this article

D’Souza, A.L., Hsiao, M.S. Error Diagnosis of Sequential Circuits Using Region-Based Model. J Electron Test 21, 115–126 (2005). https://doi.org/10.1007/s10836-005-6141-6

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-005-6141-6

Keywords

Navigation