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Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

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Abstract

In recent years, Defect Oriented Testing (DOT) has been investigated as an alternative testing method for analog circuits. In this paper, we propose a wavelet transform based dynamic supply current (IDD) analysis technique for detecting catastrophic and parametric faults in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier transform which decomposes a signal in frequency components only. Simulation results on benchmark circuits show that wavelet transform has higher fault detection sensitivity than Fourier or time-domain methods and hence, can be considered very promising for defect oriented testing of analog circuits. Effectiveness of wavelet transform based DOT amidst process variation and measurement noise is studied.

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Correspondence to Swarup Bhunia.

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This research is supported in part by MARCO GSRC under contract number SA3273JB.

Swarup Bhunia received the undergraduate degree from Jadavpur University, Calcutta, India, and the Master’s degree from the Indian Institute of Technology (IIT), Kharagpur. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, Purdue University, West Lafayette, IN.

He has worked in the EDA industry on RTL synthesis and verification since 2000. His research interest includes defect-based testing, diagnosis, noise analysis, and noise-aware design.

Arijit Raychowdhury received the B.E. degree in 2001 in electronics and telecommunication engineering from Jadavpur University, India. He is currently pursuing the Ph.D. degree in electrical and computer engineering in Purdue University, West Lafayette, IN.

He has worked as an analog circuit designer in Texas Instruments India. His research interests include device/circuit design for scaled silicon and nonsilicon devices. He has received academic excellence awards in 1997, 2000, and 2001 and Messner Fellowship from Purdue University in 2002. Mr. Raychowdhury has been awarded the Best Student Paper Award in the IEEE Nanotechnology Conference, 2003.

Kaushik Roy received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Illinois, Urbana, in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty, Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 250 papers in refereed journals and conferences, holds six patents, and is Co-Author of a book on Low Power CMOS VLSI Design (New York: Wiley). He was Guest Editor for a Special Issue on Low-Power VLSI in IEE Proceedings—Computers and Digital Techniques (July 2002). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, AT&T/Lucent Foundation Award, Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, and 2003 IEEE Nano. He is on the Editorial Board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VLSI SYSTEMS. He was Guest Editor for a Special Issue on Low-Power VLSI in IEEE DESIGN AND TEST (1994), and for the IEEE TRANSACTIONS ON VLSI SYSTEMS (June 2000).

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Bhunia, S., Raychowdhury, A. & Roy, K. Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J Electron Test 21, 147–159 (2005). https://doi.org/10.1007/s10836-005-6144-3

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  • DOI: https://doi.org/10.1007/s10836-005-6144-3

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