Abstract
In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
R. Boppana and M.M. Halldorsson, “Approximating Maximum Independent Sets by Excluding Subgraphs,” BIT Numerical Mathematics, vol. 32, no. 2, pp. 180–196, June 1992.
V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, “Techniques For Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 17, pp. 1325–1333, December 1998.
S. Gerstendorfer and H.J. Wunderlich, “Minimized Power Consumption For Scan-Based BIST,” Proc. IEEE Int'l. Test Conf., pp. 77–84, 1999.
P. Girard, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Des. Test Comput., vol. 17, issue. 3, pp. 80–90, May 2002.
P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, “Reducing Power Consumption During Test Application by Test Vector Ordering,” Proc. IEEE Int'l. Symp. Circuits and Systems, part II, pp. 296–299, 1998.
T. Huang and K. Lee, “Reduction of Power Consumption in Scan-Based Circuits During Test Application by an Input Control Technique,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 20, pp. 911–917, July 2001.
N. Jha and S. Gupta, Testing of Digital Systems, Cambridge: Cambridge University Press, 2003.
N. Nicolici, B.M. Al-Hashimi, and A.C. Williams, “Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing,” IEE Proc., Comput. Digit. Tech., vol. 147, pp.313–322, September 2002.
S. Wang and S.K. Gupta, “ATPG for Heat Dissipation Minimization During Test Application,” Proc. IEEE Int'l. Conf., pp. 250–258, October 1994.
S. Wang and S.K. Gupta, “ATPG for Heat Dissipation Minimization During Scan Testing,” Proc. 34th ACM/IEEE Design Automation Conf., July 1997, pp. 614–619.
S. Wang and S.K. Gupta, “DS-LFSR: A BIST TPG For Low Switching Activity,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, pp. 842–851, July 2002.
L. Whetsel, “Adapting Scan Architectures For Low Power Operation,” Proc. IEEE Int'l. Test Conf., pp. 863–872, 2000.
Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” Proc. 11th IEEE VLSI Test Symp., pp. 4–9, 1993.
Author information
Authors and Affiliations
Corresponding author
Additional information
Editor: C. A. Papachristou
Rights and permissions
About this article
Cite this article
Tseng, WD. Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. J Electron Test 23, 75–84 (2007). https://doi.org/10.1007/s10836-006-0098-y
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-006-0098-y