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Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

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Abstract

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions corresponding to a design are first converted into Reed–Muller forms and then implemented using delay-insensitive Reed–Muller cells. The design and layout of the Reed–Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed–Muller forms constructed by the Reed–Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit’s testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.

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Authors and Affiliations

  1. Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, 72701, USA

    Jia Di

  2. Engineering and Information Science, Texas A&M University at Texarkana, Texarkana, TX, 75501, USA

    Parag K. Lala

Authors
  1. Jia Di
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  2. Parag K. Lala
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Correspondence to Jia Di.

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Editor: M. Tehranipoor

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Di, J., Lala, P.K. Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J Electron Test 23, 175–192 (2007). https://doi.org/10.1007/s10836-006-0549-5

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  • DOI: https://doi.org/10.1007/s10836-006-0549-5

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