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A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology

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Abstract

Chemically assembled electronic nanotechnology (CAEN) is under intense investigation as a possible alternative or complement to CMOS-based computing. CAEN is a form of molecular electronics that uses directed self-assembly and self-alignment to construct electronic circuits from nanometer-scale devices that exploit quantum-mechanical effects. Although expected to have densities greater than 108 gate-equivalents/cm2, CAEN-based systems may possibly exhibit defect densities of up to 10%. The highly defective CAEN circuits will therefore require a completely new approach to manufacturing computational devices. In order to achieve any level of significant yield, it will no longer be possible to discard a device once a defect is found. Instead, a method of using defective chips must be devised. A testing strategy is developed for chemically assembled electronic nanotechnology (CAEN) that takes advantage of reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This strategy is particularly suited for regular architectures with high defect densities.

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References

  1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Piscataway, NJ: IEEE, 1990.

    Google Scholar 

  2. J.G. Brown and R.D. Blanton, “CAEN–BIST: Testing the NanoFabric,” in International Test Conference, Oct. 2004, pp. 462–471.

  3. M. Butts, A. DeHon, and S.C. Goldstein, “Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chip,” in Proceedings of International Conference on Computer Aided Design, 2002, pp. 443–440.

  4. C.P. Collier et al., “Electronically Configurable Molecular-based Logic Gates,” Science, vol. 285, pp. 391–394, July 1999.

    Article  Google Scholar 

  5. Y. Cui et al., “Diameter-controlled Synthesis of Single Crystal Silicon Nanowires,” Appl. Phys. Lett., vol. 78, pp. 2214–2216, 2001.

    Article  Google Scholar 

  6. B. Culbertson et al., “Defect Tolerance on the Teramac Custom Computer,” in Proceedings of 5th IEEE Symposium on Field-programmable Custom Computing Machines, 1997, pp. 140–147.

  7. L. Durbek and N.J. Macias, “Defect Tolerant, Fine-Grained Parallel Testing of a Cell Matrix,” in Proceedings of SPIE ITCom, vol. 4867, 2002.

  8. S.C. Goldstein and M. Budiu, “NanoFabrics: Spatial Computing Using Molecular Electronics,” in Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001, pp. 178–191.

  9. S.C. Goldstein and D. Rosewater, “Digital Logic Using Molecular Electronics,” in Proceedings of the IEEE International Solid State Circuits Conference, 2002, pp. 204–205.

  10. S. Goldstein et al., “Reconfigurable Computing and Electronic Nanotechnology,” in Proceedings of IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2003, pp. 132–142.

  11. J.R. Heath et al., “A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology,” Science, vol. 280, pp. 1716–1721, 1998 (June).

    Article  Google Scholar 

  12. J. Huang, M.B. Tahoori, and F. Lombardi, “On the Defect Tolerance of Nano-Scale Two-dimensional Crossbars,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 96–104.

  13. N.K. Jha and S. Gupta, Testing of Digital Systems, ch. 15, Cambridge, UK: Cambridge University Press, 2003.

  14. T. Kamins et al., “Chemical-vapor Deposition of Si Nanowires Nucleated by TiSi2 islands on Si,” Appl. Phys. Lett., vol. 76, pp. 562–564, 2000.

    Article  Google Scholar 

  15. Y. Luo et al., “Two-dimensional Molecular Electronics Circuits,” ChemPhysChem, vol. 3, pp. 519–525, 2002.

    Article  Google Scholar 

  16. J. Mbindyo et al., “DNA-directed Assembly of Gold Nanowires on Complementary Surfaces,” Adv. Mater., vol. 13, pp. 249–254, 2001.

    Article  Google Scholar 

  17. C. Metra et al., “Novel Technique for Testing FPGAs,” in Proceedings of Design, Automation and Test in Europe, February 1998, pp. 89–94.

  18. M. Mishra and S.C. Goldstein, “Scalable Defect Tolerance for Molecular Electronics,” in Proceedings of International Symposium on High-performance Architecture, Feb. 2002.

  19. M. Mishra and S.C. Goldstein, “Defect Tolerance at the End of the Roadmap,” in Proceedings of International Test Conference, Sept–Oct 2003, pp. 1201–1210.

  20. D.J. Pena et al., “Electrochemical Synthesis of Multi-material Nanowires as Building Blocks for Functional Nanostructures,” in MRS Symposium Proceedings, vol. 636, 2001.

  21. R. Rajsuman, “Design and Test of Large Embedded Memories: An Overview,” in IEEE Design and Test of Computers, vol. 18, May–June 2001, pp. 16–27.

  22. M.A. Reed and T. Lee, ed., Molecular Electronics, ch. 13, American Scientific, 2003.

  23. T. Rueckes et al., “Carbon Nanotube-based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94–97, 2000.

    Article  Google Scholar 

  24. R. Service, “Assembling Nanocircuits from the Bottom Up,” Science, vol. 293, no. 553, pp. 782–785, 2001.

    Article  Google Scholar 

  25. S.K. Sinha et al., “Tunable Fault Tolerance for Runtime Reconfigurable Architectures,” in IEEE Symposium on Field-programmable Custom Computing Machines, April 2000, pp. 185–192.

  26. H. Soh et al., “Integrated Nanotube Circuits: Controlled Growth and Ohmic Contacting of Single-walled Carbon Nanotubes.” Appl. Phys. Lett., vol. 75, pp. 627–629, 1999.

    Article  Google Scholar 

  27. M.R. Stan et al., “Molecular Electronics: From Devices and Interconnect to Circuits and Architecture,” in Proceedings of the IEEE, vol. 91, November 2003, pp. 1940–1957.

  28. C. Stroud et al., “Built-in Self-test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!),” in Proceedings of IEEE VLSI Test Symposium, 1996, pp. 387–392.

  29. C. Stroud, E. Lee, and M. Abramovici, “BIST-based Diagnostics for FPGA Logic Blocks,” in Proceedings of IEEE Inter-national Test Conference, 1997, pp. 539–547.

  30. M.B. Tahoori and S. Mitra, “Fault Detection and Diagnosis Techniques for Molecular Computing,” in Proceedings of NSTI Nanotechnology Conference and Trade Show, 2004, pp. 57–60.

  31. M.B. Tahoori and S. Mitra, “Defect and Fault Tolerance of Reconfigurable Molecular Computing,” in Proceedings of Field Custom Computing Machines Conference, 2004, pp. 176–185.

  32. D.E. Thomas and P. Moorby, The Verilog Hardware Description Language, Kluwer, Dordrecht, The Netherlands, 1991.

  33. F. Toth, “Get the EasyPath Solution,” Xcell Journal, Summer 2003.

  34. S. Venkataraman and S.B. Drummonds, “Poirot: Applications of a Logic Fault Diagnosis Tool,” IEEE Design and Test of Computers, vol. 18, no. 1, pp. 19–30, 2001.

    Article  Google Scholar 

  35. Z. Wang and K. Chakrabarty, “Built-in Self-test of Molecular Electronics-Based Nanofabrics,” in Proceedings of European Test Symposium, May 2005, pp. 168–173.

  36. S.J. Wang and T.M. Tsai, “Test and Diagnosis of Faulty Logic Blocks in FPGAs,” IEE Proc. E, vol. 146, pp. 100–106, March 1999.

    Google Scholar 

  37. E. Winfree et al., “Design and Self-assembly of Two-dimensional DNA Crystals,” Nature, vol. 394, pp. 539–544, 1998.

    Article  Google Scholar 

  38. Y. Xia et al., “Unconventional Methods for Fabricating and Patterning Nanostructures,” Chem Rev., vol. 99, pp. 1823–1848, 1999.

    Article  Google Scholar 

  39. M.M. Ziegler and M.R. Stan, “A Case for CMOS/Nano Co-design,” in Proceedings of the International Conference on Computer-aided Design, November 2002, pp. 348–352.

  40. M.M. Ziegler and M.R. Stan, “The CMOS/Nano Interface from a Circuits Perspective,” in Proceedings of the International Symposium on Circuits and Systems, May 2003, pp. 904–907.

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Authors and Affiliations

  1. Center for Silicon System Implementation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213, USA

    Jason G. Brown & R. D. Blanton

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  1. Jason G. Brown
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  2. R. D. Blanton
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Correspondence to Jason G. Brown.

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Editor: M. Tehranipoor

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Brown, J.G., Blanton, R.D. A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. J Electron Test 23, 131–144 (2007). https://doi.org/10.1007/s10836-006-0552-x

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  • DOI: https://doi.org/10.1007/s10836-006-0552-x

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