Abstract
As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach. In this paper we describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. If extended to more complex circuits, our approach could lead to a paradigm shift in computing architecture without abandoning the dominant silicon CMOS technology.
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Nepal, K., Bahar, R.I., Mundy, J. et al. Designing Nanoscale Logic Circuits Based on Markov Random Fields. J Electron Test 23, 255–266 (2007). https://doi.org/10.1007/s10836-006-0553-9
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DOI: https://doi.org/10.1007/s10836-006-0553-9