Abstract
Disturb faults are considered one the most important failure modes in non volatile memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization. In this paper, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs and to create a reduced fault list. To demonstrates its effectiveness, the method was used to create minimized fault lists for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.
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Editor: K. K. Saluja
This work was supported by Kuwait University Research Grant Number EO 01/04.
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Mohammad, M.G., Terkawi, L. Techniques for Disturb Fault Collapsing. J Electron Test 23, 363–368 (2007). https://doi.org/10.1007/s10836-006-0629-6
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DOI: https://doi.org/10.1007/s10836-006-0629-6