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MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

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Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Yonsei University, 134, Shinchon-Dong Seodaemoon-Gu, Seoul, South Korea

    Sunghoon Chun, Sunghoon Chun, Yongjoon Kim & Sungho Kang

Authors
  1. Sunghoon Chun
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  2. Yongjoon Kim
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  3. Sungho Kang
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Correspondence to Sunghoon Chun.

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Editor: K. K. Saluja

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Chun, S., Kim, Y. & Kang, S. MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. J Electron Test 23, 357–362 (2007). https://doi.org/10.1007/s10836-006-0630-0

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  • DOI: https://doi.org/10.1007/s10836-006-0630-0

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