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A Self Test Program Design Technique for Embedded DSP Cores

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Abstract

This paper describes a self test program design technique for embedded DSP cores. The method requires minimal knowledge of the core’s internals and minimal insertion of external LFSR hardware, without scan insertions. The test program consists of a small set of instructions which operate iteratively on pseudorandom data generated by the LFSRs to fully test the DSP core components. The method uses instruction-based test metrics and a program template as a blueprint to generate the test program. The self test scheme has been successfully applied on an industrial-strength DSP core and the results compare favorably to other methods using ATPG and pseudorandom BIST.

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Authors and Affiliations

  1. Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, OH, 44106

    Hani Rizk, Chris Papachristou & Francis Wolff

Authors
  1. Hani Rizk
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  2. Chris Papachristou
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  3. Francis Wolff
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Corresponding author

Correspondence to Hani Rizk.

Additional information

Editor: C.E. Stroud

Hani Rizk received his B.S./M.S. in Computer Engineering at Case Western Reserve University in 2002. He currently works at Intel Corporation in Oregon.

Chris Papachristou has a Ph.D. from Johns Hopkins University. He is currently a Professor of Computer Engineering at Case Western Reserve University. His research interests are in Embedded Systems, CAD, Adaptive Hardware, Testing and Fault Tolerance.

Francis G. Wolff has a Ph.D. from Case Western Reserve University in Computer Engineering and is also a researcher in the area of computer engineering.

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Rizk, H., Papachristou, C. & Wolff, F. A Self Test Program Design Technique for Embedded DSP Cores. J Electron Test 22, 71–87 (2006). https://doi.org/10.1007/s10836-006-5549-y

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  • DOI: https://doi.org/10.1007/s10836-006-5549-y

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