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A Gated Clock Scheme for Low Power Testing of Logic Cores

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Abstract

Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.

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Author notes

  1. Yannick Bonhomme

    Present address: CEA-LIST, Saclay, France

  2. Loïs Guiller

    Present address: Synopsys Inc., Mountain View, USA

Authors and Affiliations

  1. Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506/Université Montpellier II / CNRS, 161, rue Ada, 34392, Montpellier Cedex 05, France

    Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch & Arnaud Virazel

Authors
  1. Yannick Bonhomme
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  2. Patrick Girard
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  3. Loïs Guiller
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  4. Christian Landrault
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  5. Serge Pravossoudovitch
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  6. Arnaud Virazel
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Corresponding author

Correspondence to Yannick Bonhomme.

Additional information

This work has been partially funded by the French government under the framework of the MEDEA+ A503 “ASSOCIATE” European project. Preliminary versions of this work were presented at VTS 2001 [18] and ATS 2001 [1].

Yannick Bonhomme received a M.Sc. degree in Electrical Engineering (1998) and a Ph.D. degree in Microelectronics (2003) from the University of Montpellier (France). From 2003 to 2004, he spent one year as full researcher at Nara institute of Science and Technology (NAIST) in Japan. He is now a researcher at CEA-LIST (Commissariat à l’Energie Atomique - Laboratoire d’Intégration des Systèmes et des Technologies, http://www-list.cea.fr) Saclay, France. His research interests are in test, design for test, online test and BIST.

Patrick Girard received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier - France). Patrick Girard is the Editor-in-Chief of the ASP Journal of Low Power Electronics, and an Associate Editor of the IEEE Transactions on Computers. He is on the technical program committee of the ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IFIP VLSI-SOC Conference, IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE International On-Line Testing Symposium (IOLTS), IEEE Asian Test Symposium (ATS), IEEE Reconfigurable Architecture Workshop (RAW), IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS) and IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS). He has served as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing (EUC) in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications (DELTA) in 2006. Patrick Girard has been involved in several European research projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+ NanoTEST) and has managed several industrial research contracts. His research interests include the various aspects of digital testing, with special emphasis on DfT, BIST, diagnosis, delay testing, FPGA testing, power-aware testing and memory testing. He has published 1 book, 25 journal papers, and more than 80 conference and symposium papers on these fields.

Loïs Guiller was born in 1973. He received the MSc degree in Electrical Engineering in 1997 and the PhD degree in Microelectronics in 2000 from the University of Montpellier, France. His research interests include VLSI design and testing. He is currently a Research and Development Engineer at Synopsys, Mountain View, USA.

Christian Landrault received the Certified Engineering degree from the Higher National School for Aeronautical Constructions (ENSICA), Toulouse, France in 1970, the Doctor in Engineering degree in Automatic Control, and the Doctor es-sciences degree in Computer Science from the National Polytechnic Institute of Toulouse, in 1973 and 1977, respectively. He is currently a “Directeur de Recherche" at CNRS ("National scientific Research Center"). He joined LAAS-CNRS in Toulouse in 1970. From 1970 to 1980, he worked on self checking circuits, dependability architecture and dependability evaluation of digital systems.Since 1980, he is working with LIRMM (“Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier", http://www.lirmm.fr) where he was head of the Microelectronics research Department till January 2001. C. Landrault’s scientific interests include fault modelling, digital and memory testing, fault simulation, ATPG, design for testability and BIST. Christian Landrault has authored or co-authored over 150 papers for international and national journals and conferences and has supervised 27 PhD dissertations on Electronic Design Automation. Dr. Landrault is serving most of the test conference Programme Committees (ITC, VTS, ICCAD, DATE, ATS, ETS) and is a member of the editorial board of the Journal of Electronic Testing and Applications (Kluwer). Dr. Landrault has founded the European Test Workshop, and has served as General Chair in 1996, and as Programme Chair in 1998 and 1999. ETW became the European Test Symposium in 2004 with Dr Landrault chairing its steering committee. Dr Landrault has been the elected chair of the European group of the Test Technology Technical Council of the IEEE Computer Society from 1998 to 2001. He is the actual Chair of the European Sub-committee of the International Test Conference Programme Committee. Dr. Landrault is a Golden Core Member of the IEEE Computer Society.

Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier). He got the PhD degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the “doctorat d’état” degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several PhD dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).

Arnaud Virazel was born in Montpellier (France) in 1974. He received the B.Sc. (1995), the M.Sc. (1997) degrees in Electrical Engineering and the PhD (2001) degree in Microelectronics, all from the University of Montpellier. He is currently Assistant Professor at the University of Montpellier, and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier - France). He is on the technical program committee of the International Conference on Embedded And Ubiquitous Computing (EUC) in 2005. Arnaud Virazel has been involved in several European research projects (MEDEA+ ASSOCIATE, MEDEA+ NanoTEST). His research interests include the various aspects of digital testing, with special emphasis on DfT, BIST, diagnosis, delay testing, power-aware testing and memory testing.

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Bonhomme, Y., Girard, P., Guiller, L. et al. A Gated Clock Scheme for Low Power Testing of Logic Cores. J Electron Test 22, 89–99 (2006). https://doi.org/10.1007/s10836-006-6259-1

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