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Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

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Abstract

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Tsing-Hua University, Taiwan, ROC

    Yu-Chiun Lin & Shi-Yu Huang

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  1. Yu-Chiun Lin
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  2. Shi-Yu Huang
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Part of this work has ever appeared in the proceedings of Asian Test Symposium in 2003.

Yu-Chiun Lin received his BS degrees in Electrical Engineering from National Central University in 2000, and MS degree from Electrical Engineering of National Tsing Hua University in 2002. Since then, he has been with Ali Corporation as a design engineer. His current interests include the design of USB controllers and imaging periperals.

Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests include CMOS image sensor design, low-power memory design, power estimation, and fault diagnosis methodologies.

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Lin, YC., Huang, SY. Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. J Electron Test 22, 151–159 (2006). https://doi.org/10.1007/s10836-006-7143-8

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  • DOI: https://doi.org/10.1007/s10836-006-7143-8

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