Abstract
For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.
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Editor: K.K. Saluja
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Seuring, M. Combining Scan Test and Built-in Self Test. J Electron Test 22, 297–299 (2006). https://doi.org/10.1007/s10836-006-8950-7
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DOI: https://doi.org/10.1007/s10836-006-8950-7