Skip to main content
SpringerLink
Log in

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD). This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary. In fact, the approach is a pure hardware solution to fault diagnosis. We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits. The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis. This speed-up is important, especially, when the on-line diagnosis of safety–critical systems is of concern.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Abramovici M (1981) A maximal resolution guided-probe testing algorithm. In: Proc. of ACM/IEEE Design Automation Conference, pp 189–195

  2. Abramovici M, Breuer MA (1980) Fault diagnosis based on effect-cause analysis. In: Proc. of ACM/IEEE Design Automation Conference, pp 69–76

  3. Abramovici M, Menon P (1997) Fault simulation on reconfigurable hardware. In: Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp 182–190, 16–18 April 1997

  4. Abramovici M, Saab DG (1997) Satisfiability on reconfigurable hardware. In: Int’l. Workshop on Field-Programmable Logic and Applications, September 1997

  5. Abramovici M, Breuer MA, Friedman AD (1995) Digital systems testing and testable design. IEEE Press

  6. Augusto J, Almeida C, Neto H (2003) A Modular reconfigurable architecture for efficient fault simulation in digital circuits. In: Proc. of Field-Programmable Logic and Aplications, Springer, Berlin

  7. Burgun L, Reblewski F, Fenelon G, Berbier J, Lepape O (1996) Serial fault emulation. In: Proceedings of ACM/IEEE Design Automation Conference, pp 801–806

  8. Butts JBM, Varghese J (1992) An efficient logic emulation system. In: Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp 138–141, 11–14 October 1992

  9. Camurati P, Medina D, Prinetto P, Reorda MS (1990) A diagnostic test pattern generation algorithm. In: Proc. of IEEE Int’l Test Conf., IEEE Computer Society Press, pp 52–58, Sept. 1990

  10. Cheng K-T, Huang S-Y, Dai W-J (1999) Fault emulation: a new methodology for fault grading. IEEE Trans Comput-aided Des Integr Circuits Syst 18:1487–1495

    Article  Google Scholar 

  11. Cox H, Rajski J (1988) A method of fault analysis for test generation and fault diagnosis. IEEE Trans on CAD of Integrated Circuits and Systems, pp 813–833

  12. Hartanto I, Venkataraman S, Fuchs WK, Rudnick EM, Patel JH, Chakravarty S (2001) Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Transact Des Automat Electron Syst 6:471–489

    Article  Google Scholar 

  13. Kocan F, Saab DG (1998) Dynamic fault diagnosis for sequential circuits on reconfigurable hardware, in Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, 5–7, pp 214–215, October

  14. Kocan F, Saab DG (1999) Dynamic fault diagnosis on reconfigurable hardware. In: Proceedings of ACM/IEEE Design Automation Conference, pp 691–696

  15. Kocan F, Saab DG (2001) ATPG for combinational circuits on configurable hardware. IEEE Trans Very Large Scale Integr (VLSI) Syst 9:117–129

    Article  Google Scholar 

  16. Kubiak K, Parkes S, Fuchs WK, Saleh R (1992) Exact evaluation of diagnostic test resolution. In: Proc. of ACM/IEEE Design Automation Conference, pp 347–352

  17. Miremadi SG, Ejlali A (2003) Switch level fault emulation. In: Proc. of Field-Programmable Logic and Aplications. Springer, Berlin

  18. Pagarani T, Kocan F, Saab DG, Abraham JA (2000) Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. In: Proceedings of IEEE Custom Integrated Circuits Conference, pp 147–150

  19. Parreira A, Santos M, Sousa J (2003) Fault simulation using partially reconfigurable hardware. In: Proc. of Field-Programmable Logic and Aplications. Springer, Berlin

  20. Paul WKF, Ryan G, Rawatt S (1991) Two-stage fault location. In: Proc. of IEEE Int’l Test Conf., pp 963–968

  21. Pomeranz I, Reddy S (1992) On the generation of small dictionaries for fault location. In: Proc. of IEEE/ACM Int’l Conf. on CAD, pp 272–279

  22. Pomeranz I, Reddy SM (1997) On dictionary-based fault location in digital logic circuits. IEEE Trans Comput 46:48–59

    Article  Google Scholar 

  23. Rashid A, Leonard J, Mangione-Smith WH (1998) Dynamic circuit generation for solving specific problem instances of boolean satisfiability. In: Pocek KL, Arnold J (eds) IEEE Symposium on FPGAs for Custom Computing Machines. IEEE Computer Society Press, Los Alamitos, CA, pp 196–204

  24. Reorda MS, Violante M (2003) Emulation-based analysis of soft errors in deep sub-micron circuits. In: Field-Programmable Logic and Applications. Springer, Berlin

  25. Richman J, Bowden KR (1985) The modern fault dictionary. In: Proc. of IEEE Int’l Test Conf, pp 696–702

  26. Ryan PG, Fuchs WK, Pomeranz I (1993) Fault dictionary compression and equivalence class computation for sequential circuits. In: Proc. of IEEE/ACM Int’l Conf. on CAD, pp 508–511

  27. Saab DG, Saab YG, Abraham JA (1986) Automatic test vector cultivation for sequential vlsi circuits using genetic algorithms. IEEE Trans on CAD of Integrated Circuits and Systems 15:1278–1285

    Article  Google Scholar 

  28. Suyama T, Yokoo M, Sawada H (1996) Solving satisfiability problems on fpgas. In: Proc. Intn’l. Workshop on Field-Programmable Logic and Applications

  29. Saab DG, Kocan F, Abraham JA (2002) Massively parallel/reconfigurable emulation model for the d-algorithm. In: Manfred Glesner PZ, Renovell M (eds) Proceedings of 12th International Conference on Field-Programmable Logic and Applications, Lecture Notes in Computer Science 2438, Springer, pp 1172–1176, 2–4 September 2002

  30. XILINX, Vertex-ii pro complete data sheet, in http://www.xilinx.com

  31. Zhong P, Martonosi M, Ashar P, Malik S (1998) Accelerating boolean satisfiability with configurable hardware. In: Pocek KL, Arnold J (eds) IEEE Symposium on FPGAs for Custom Computing Machines. IEEE Computer Society Press, Los Alamitos, CA, pp 186–195

Download references

Author information

Authors and Affiliations

  1. Computer Science and Engineering, Southern Methodist University, Dallas, TX, USA

    Fatih Kocan

  2. Electrical Eng. and Computer Science, Case Western Reserve University, Cleveland, OH, USA

    Daniel G. Saab

Authors
  1. Fatih Kocan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Daniel G. Saab
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Fatih Kocan.

Additional information

Responsible Editor: C.-W. Wu

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kocan, F., Saab, D.G. Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. J Electron Test 23, 405–420 (2007). https://doi.org/10.1007/s10836-007-5009-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-007-5009-3

Keywords

Search

Navigation