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A System-layer Infrastructure for SoC Diagnosis

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Abstract

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

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Authors and Affiliations

  1. Dipartimento di Automatica e Informatica, Politecnico di Torino, Turin, Italy

    P. Bernardi, M. Grosso, M. Rebaudengo & M. Sonza Reorda

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  1. P. Bernardi
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  2. M. Grosso
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  3. M. Rebaudengo
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  4. M. Sonza Reorda
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Correspondence to P. Bernardi.

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Responsible Editor: C. Landrault

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Bernardi, P., Grosso, M., Rebaudengo, M. et al. A System-layer Infrastructure for SoC Diagnosis. J Electron Test 23, 389–404 (2007). https://doi.org/10.1007/s10836-007-5014-6

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  • DOI: https://doi.org/10.1007/s10836-007-5014-6

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