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Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy

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Abstract

This paper presents simulations of three different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important trade-offs between supply voltage, redundancy and yield are revealed, and V DD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2, in 90 nm CMOS.

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  1. Department of Informatics, University of Oslo, Postbox 1080, Blindern, 0316, Oslo, Norway

    Kristian Granhaug & Snorre Aunet

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  1. Kristian Granhaug
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  2. Snorre Aunet
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Correspondence to Kristian Granhaug.

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Responsible Editor: N. A. Touba

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Granhaug, K., Aunet, S. Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J Electron Test 24, 157–163 (2008). https://doi.org/10.1007/s10836-007-5027-1

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