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A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy

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Abstract

Built-in self-repair (BISR) technique is a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) component is a core component in a BISR design. This paper presents a BIRA scheme for RAMs with two-level redundancy, i.e., spare rows, spare columns, and spare words. A compressed local bitmap is used to collect faulty information for redundancy allocation. Then an efficient redundancy analysis algorithm based on the compressed local bitmap is proposed to allocate redundancy. Experimental results show that the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the proposed redundancy analysis algorithm approaches to that of the exhaustive search algorithm. Also, area overhead of the proposed BIRA scheme is low. It is only about 2% for an 8K × 64-bit RAM with three spare rows, three spare columns, and two spare words.

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Acknowledgment

This work was supported in part by National Science Council, Taiwan, R.O.C., under contract NSC 96-2221-E-008-094 and MOEA, Taiwan, R.O.C., under contract 96-EC-17-A-01-S1-002.

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  1. Advanced Reliable Systems (ARES) Laboratory, Department of Electrical Engineering, National Central University, Jhongli, Taiwan, 320

    Da-Ming Chang, Jin-Fu Li & Yu-Jen Huang

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  1. Da-Ming Chang
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  2. Jin-Fu Li
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Correspondence to Jin-Fu Li.

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Responsible Editor: N. A. Touba

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Chang, DM., Li, JF. & Huang, YJ. A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J Electron Test 24, 181–192 (2008). https://doi.org/10.1007/s10836-007-5032-4

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  • DOI: https://doi.org/10.1007/s10836-007-5032-4

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