Abstract
While integrated circuits of ever increasing size and complexity necessitate larger test sets for ensuring high test quality, the consequent test time and data volume reflect into elevated test costs. Test data compression solutions have been proposed to address this problem by storing and delivering stimuli in a compressed format. The effectiveness of these techniques, however, strongly relies on the distribution of the specified bits of test vectors. In this paper, we propose a scan cell partitioning technique so as to ensure that specified bits are uniformly distributed across the scan slices, especially for the test vectors with higher density of specified bits. The proposed scan cell partitioning process is driven by an integer linear programming (ILP) formulation, wherein it is also possible to account for the layout and routing constraints. While the proposed technique can be applied to increase the effectiveness of any combinational decompression architecture, in this paper, we present its application in conjunction with a fan-out based decompression architecture. The experimental results also confirm the compression enhancement of the proposed methodology.
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Notes
The absence of physical location information in the academic ISCAS89 benchmark circuits prevents us from applying the incremental approach that we have presented in Section 3.4. With no loss of generality, we assume in our experiments that alphabetical ordering of the scan cells correlates to their physical positions in the design.
References
Bayraktaroglu I, Orailoglu A (2001) Test volume and application time reduction through scan chain concealment. In: DAC, pp 151–155
Bayraktaroglu I, Orailoglu A (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In: VTS, pp 113–118
Garey M, Johnson DS (1979) Computers and intractability: a guide to the theory of NP-completeness. Freeman
Hamzaoglu I, Patel JH (1999) Reducing test application time for full scan embedded cores. In: FTCS, pp 260–267
Koenemann B (1991) LFSR-coded test patterns for scan designs. In: ETC, pp 237–242
Lee HK, Ha DS (1993) On the generation of test patterns for combinational circuits. Technical Report 12-93, Department of Electrical Eng., Virginia Polytechnic Institute and State University
Marquinho V, Marques-Silva J (2000) BSOLO 0-1 ILP Solver, http://sat.inesc.pt/bsolo/
Mitra S, Kim KS (2006) XPAND: an efficient test stimulus compression technique. IEEE TCOMP 55(2):163–173, February
Pandey AR, Patel JH (2002) Reconfiguration technique for reducing test time and test data volume in illinois scan architecture based designs. In: VTS, pp 9–15
Rajski J, Kassab M, Mukherjee N, Tamarapalli N, Tyzser J, Qian J (2003) Embedded deterministic test for low-cost manufacturing. IEEE Des Test 20(5):58–66, September
Samaranayake S, Gizdarski E, Sitchinava N, Neuveux F, Kapur R, Williams TW (2003) A reconfigurable shared scan-in architecture. In: VTS, pp. 9–14
Shah MA, Patel JH (2004) Enhancement of the Illinois scan architecture for use with multiple scan inputs. In: ISVLSI, pp 167–172
Sitchinava N, Samaranayake S, Kapur R, Gizdarski E, Neuveux F, Williams TW (2004) Changing the scan enable during shift. In: VTS, pp 73–78
Tang H, Reddy SM, Pomeranz I (2003) On reducing test data volume and test application time for multiple scan chain designs. In: ITC, pp 1070–1088
Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test 23(4):294–303, April
Wang LT, Wen X, Furukawa H, Hsu FS, Lin SH, Tsai SW, Abdel-Hafiz KS, Wu S (2004) VirtualScan: a new compressed scan technology for test cost reduction. In: ITC, pp 916–925
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Sinanoglu, O. Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. J Electron Test 24, 439–448 (2008). https://doi.org/10.1007/s10836-007-5039-x
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DOI: https://doi.org/10.1007/s10836-007-5039-x