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Bilateral Testing of Nano-scale Fault-Tolerant Circuits

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Abstract

As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS’85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.

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References

  1. Al-Assad H, Lee R (2002) Simulation-based approximate global fault collapsing. In: Proc of international conf on VLSI, pp 72–77

  2. Amyeen E, Pomeranz I, Kent Fuchs W (2002) Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits. In: Proc VLSI test symp, pp 181–186

  3. Chen T, Hajj IN (1997) A hierarchical bridging fault extraction approach for vlsi circuit layouts. In: Proc int symp on VLSI tech, pp 348–354, June 1997

  4. de Geus AJ (1986) Logic synthesis and optimization benchmarks for the 1986 design automation conference. In: DAC ’86: Proceedings of the 23rd ACM/IEEE conference on design automation, p 78

  5. Esaki L, Tsu R (1970) Superlanice and negative differential conductivity in semiconducton. IBM J Res Develop 14:61–65

    Article  Google Scholar 

  6. Friedman AD, Abramovici M, Breuer MA (1994) Digital systems testing & testable design. Wiley, rev. print edition, September

  7. Fujiwara T, Shimono H (1983) On the acceleration of test generation algorlthms. IEEE Trans Comput C-32:1137–1144, December

    Article  Google Scholar 

  8. Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Computers C-30(3):215–222, March

    Article  MathSciNet  Google Scholar 

  9. Goldstein L (1980) Controllability/observability analysis of digital circuits. IEEE Trans Circuits Syst CAS-26:685–693, September

    Google Scholar 

  10. Grüning T, Mahlstedt U, Koopmeiners H (1991) Diatest: a fast diagnostic test pattern generator for combinational circuits. In: Proc international conf computer aided design, pp 194–197

  11. Gupta P, Jha NK, Lingappan L (2006) Test generation for combinational quantum cellular automata (QCA) circuits. In: Design, automation and test in Europe, pp 311–316

  12. Han J (2004) Fault-tolerant architectures for nanoelectronic and quantum devices. Doctoral Dissertation, Delft University of Technology, http://www.qi.tnw.tudelft.nl/~jie

  13. Hartanto I, Boppana V, Kent Fuchs W (1996) Diagnostic fault equivalence identification using redundancy information and structural analysis. In: Proc international test conf, pp 294–302

  14. Lala PK (1985) Fault tolerant and fault testable hardware design. Prentice-Hall, January

  15. Lala PK (2001) Self-checking and fault-tolerant digital design, 1st edn. Morgan Kaufmann, January

  16. Likharev KK (1999) Single-electron devices and their applications. Proc IEEE 87(4):606–632, April

    Article  Google Scholar 

  17. Lioy A (1992) Advanced fault collapsing. IEEE Des Test Comput 9(1):64–71, March

    Article  Google Scholar 

  18. Mitra S, Saxena NR, McCluskey EJ (2000) Fault escapes in duplex systems. In: Proc VLSI test symp, pp 453–458

  19. Nakanishi T, Bachtold A, Hadley P, Dekker C (2001) Logic circuits with carbon nanotube transistors. Science 294:1317–1320

    Article  Google Scholar 

  20. Nepal K, Bahar RI, Mundy JL, Patterson WR, Zaslavsky A (2006) Optimizing noise-immune nanoscale circuits using principles of Markov random fields. In: ACM Great Lakes Symposium on VLSI, pp 149–152

  21. Prasad AVSS, Agrawal VD, Atre MV (2002) A new algorithm for global fault collapsing into equivalence and dominance sets. In: Proc international test conf, pp 391–397, October

  22. Rao W, Orailoglu A, Karri R (2006) Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance. In: Proc VLSI test symp, pp 214–221

  23. Siewiorek DP (1975) Reliability modeling of compensating module failures in majority voted redundancy. IEEE Trans Computers 24(5):525–533

    Article  MATH  MathSciNet  Google Scholar 

  24. Stan MR, Franzon PD, Goldstein SC, Lach JC, Ziegler MM (2003) Molecular electronics: from devices and interconnect to circuits and architecture. Proc IEEE 91:1940–1957, November

    Article  Google Scholar 

  25. Stanojevic Z, Walker DMH (2001) Fedex - a fast bridging fault extractor. In: Proc international test conf, pp 696–703

  26. Stroud CE, Barbour AE (1989) Design for testability and test generation for static redundancy system level fault-tolerant circuits. In: Proc international test conf, pp 812–818

  27. Tougaw PD, Lent CS (1994) Logical devices implemented using quantum cellular automata. J Appl Phys 75:1818–1825, February

    Article  Google Scholar 

  28. Wang Z, Chakrabarty K (2005) Built-in self-test of molecular electronics-based nanofabrics. In: 10th IEEE European test symposium, Los Alamitos, CA, USA, IEEE Computer Society, pp 168–173

  29. Zachariah ST, Chakravarty S (2000) A scalable and efficient methodology to extract two node bridges from large industrial circuits. In: Proc international test conf, pp 750–759

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, 24061, USA

    Lei Fang & Michael S. Hsiao

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  1. Lei Fang
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  2. Michael S. Hsiao
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Correspondence to Lei Fang.

Additional information

Responsible Editor: N. A. Touba

Supported in part by NSF Grants 0196470, 0305881 and 0417340.

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Fang, L., Hsiao, M.S. Bilateral Testing of Nano-scale Fault-Tolerant Circuits. J Electron Test 24, 285–296 (2008). https://doi.org/10.1007/s10836-007-5041-3

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  • DOI: https://doi.org/10.1007/s10836-007-5041-3

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