A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

Abstract

During back-end manufacturing process of IC, intervention of spot defects induces extra and missing material of interconnects causing circuit failures. Interconnect narrowing occurs when spot defects induce interconnects missing material without resulting in a complete cut. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, an innovative layout sensitivity model accounting for “narrow” defects is derived. The paper also pioneers estimation of the probability of narrow interconnects in the die. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technologies down to 32 nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.

Appendix A. Complete derivation of layout sensitivity model for narrow defects

In this appendix, we present a thorough derivation of the layout sensitivity model for narrow defects. The model is based on the layout sensitivity presented in [16].

Some assumptions are made in order to simplify the derivation of the model. First, we assume that interconnect routing is performed using a grid based approach. The layout grid consists of channels that can be either empty or occupied by interconnects. We also assume that the routing of different interconnects are independent of each other. These assumptions are made without loss of generality of the model since the same assumptions are also made in most yield analysis tools to perform critical area studies.

We define channel density, d, as the probability of a random channel to be filled. Therefore, the probability of a random channel to be empty is given by (1 − d). Channel density, d, can be deduced from the metal density, D, using the following expression:

$$D = d\frac{w}{{w + s}},$$

(7)

where w and s are the interconnect width and spacing, respectively.

It is important to note that a defect of a specific size r does not always cover the same number of channels. In fact, the number of channels covered by a defect depends on the size of the defect as well as its location. Therefore, to determine the probability for a defect of size r to cause an open defect, we need to find out the possible number of channels that can be covered and the chances for each case to occur. This is achieved by moving the defect a distance of (w + s) away from its original location, with steps equal to the smallest unit of distance, while checking the number of covered channels for every different location. The probability for the defect to cover a certain number of channels, N, is the ratio of all locations at which the defect covers N channels to the distance (w + s)¹ i.e. the total number of possible locations of the defect.

Let m be the minimum number of channels covered by the defect. It is recommended to refer to Fig. 14 for a better understanding of the derivation of the model. The defect covers a minimum number of channels when its leftmost (rightmost) edge coincides with the right (left) edge of the interconnect with the minimum width, w _n , units of distance to the right (left) of the left (right) edge of a particular channel. At this point, the partially covered channel (channel B in example of Fig. 14) is not considered as a cut channel and will be referred to as the first channel. A part of the defect with distance (w − w _n ) is needed to cover the first channel and the remaining part of distance (r − (w − w _n )) is to cover the minimum number of channels m (refer to Fig. 14).

Fig. 14

Example of a defect at a location covering the minimum number of channel m. In this case, the defect covers channels C and D, and therefore, m is equal to 2

The last channel (channel D in the example of Fig. 14) needs a distance of $\left( {w - w_n + s} \right)$ to be covered. Other channels i.e. excluding first and last channels that we call m ₁, need a distance of (w + s) to be covered by the defect and cause a channel cut. The number of channels m ₁ that can be covered by the width (r − (w − w _n )) of the defect is determined as follows:

$$m_1 = \left\lfloor {\frac{{r - \left( {w - w_n } \right)}}{{w + s}}} \right\rfloor .$$

(8)

For the remaining part of the defect that neither covers one of the m1 channels nor covers the first channel, which is equal to $r - \left( {w - w_n } \right) - m_1 \left( {w + s} \right)$, we check if it cuts an additional channel (the last channel). The additional channel is considered as cut if the defect covers more than (w − w _n ) of its total width. Therefore, m can be written as follows:

$$\matrix {m = m_1 + \left[ {\left\lfloor {\frac{{r - \left( {w - w_n } \right) - m_1 \left( {w + s} \right)}}{{w - w_n + s}}} \right\rfloor >0} \right]} \\ { = \left\lfloor {\frac{{r - \left( {w - w_n } \right)}}{{w + s}}} \right\rfloor + \left[ {\left\lfloor {\frac{{r - \left( {w - w_n } \right) - \left\lfloor {\frac{{r - \left( {w - w_n } \right)}}{{w + s}}} \right\rfloor \left( {w + s} \right)}}{{w - w_n + s}}} \right\rfloor >0} \right]} \ ,\matrix {m = m_1 + \left[ {\left\lfloor {\frac{{r - \left( {w - w_n } \right) - m_1 \left( {w + s} \right)}}{{w - w_n + s}}} \right\rfloor >0} \right]} \\ { = \left\lfloor {\frac{{r - \left( {w - w_n } \right)}}{{w + s}}} \right\rfloor + \left[ {\left\lfloor {\frac{{r - \left( {w - w_n } \right) - \left\lfloor {\frac{{r - \left( {w - w_n } \right)}}{{w + s}}} \right\rfloor \left( {w + s} \right)}}{{w - w_n + s}}} \right\rfloor >0} \right]} \ ,$$

(9)

where [x] is Iverson’s convention that evaluates to 1 if x is true, and 0 if x is false.

Now, we start moving the defect toward cutting the first channel with steps equal to the smallest unit of distance. We assume that the movement is always made to the left to simplify the explanation. At this stage, (m + 1) channels are cut, i.e. the first channel as well as all other channels that were considered in the minimum number m of channels. (m + 1) channels remains cut for a distance of $r - \left( {w - w_n } \right) - \left( {w + s - w_n } \right) - \left( {m - 1} \right)\left( {w + s} \right)$, i.e. width of defect minus width of defect to cover first channel minus width of defect needed to cover the last channel minus width of defect needed to cover all other channels (m − 1 channels) as depicted by Fig. 14. This distance can be expressed by $r - w - m\left( {w + s} \right) + 2w_n$.

After the defect is moved $r - w - m\left( {w + s} \right) + 2w_n$, the last channel that was considered in the m channels will be uncovered instantly. There will be m cut channels until the left (right) edge of the defect coincides with the right (left) edge of the interconnect with the minimum width i.e. w _n units of distance to the right (left) of the left (right) edge of the channel neighboring the first channel to its left (right). The defect would have moved for $\left( {w + s} \right) - \left( {r - w - m\left( {w + s} \right) + 2w_n } \right)$, which evaluates to $2w + s + m\left( {w + s} \right) - r - 2w_n$.

Thus, the defect either covers m channels with a probability of

$$\frac{{2w + s + m\left( {w + s} \right) - r - 2w_n }}{{w + s}},$$

(10)

or (m + 1) channels with a probability of

$$\frac{{r - w - m\left( {w + s} \right) + 2w_n }}{{w + s}}$$

(11)

The probability for the chip to overcome a defect that covers N channels is the probability for the N consecutive channels to be empty, which is (1 − d)^N. Therefore, in the general case, the probability for the chip to overcome a defect of size r, i.e., the probability of survival, referred to as P _s, is the product of the probability of a defect to cover a number N of channels by (1 − d)^N summed up for all possible number of channels that the defect can cover. Since the defect can either cover m channels or (m + 1) channels as demonstrated earlier, then P _NF is computed as in Eq. 12 (shown at the bottom of the page).

The layout sensitivity S _n is defined to be the probability of chip failure P _F. Thus, the layout

$$P_{\text{s}} = \frac{{2w + s + m\left( {w + s} \right) - r - 2w_n }}{{w + s}} \times \left( {1 - d} \right)^m + \frac{{r - w - m\left( {w + s} \right) + 2w_n }}{{w + s}} \times \left( {1 - d} \right)^{m + 1} $$

(12)

sensitivity is modeled as in Eq. 13 (shown at the bottom of the page).

$$S_n = P_{\text{F}} = 1 - P_{\text{s}} = 1 - \left( {\begin{array}{*{20}l} {\frac{{2w + s + m\left( {w + s} \right) - r - 2w_n }}{{w + s}} \times } \hfill & {\left( {1 - d} \right)^m } \hfill \\ { + \frac{{r - w - m\left( {w + s} \right) + 2w_n }}{{w + s}} \times } \hfill & {\left( {1 - d} \right)^{m + 1} } \hfill \\ \end{array} } \right)$$

(13)