How Many Test Vectors We Need to Detect a Bridging Fault?

Abstract

The growing dispersion of ICs’ parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC’s parameters. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC’s parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks.

Appendix

In order to show that a local prime test (t) is also essential (in case only the propagation through a single FO gate is allowed), we will show that it is possible to construct a configuration of circuit parameters which can be detected only by t.

We will suppose that: (a) the ON resistance of MOS transistors is positive; (b) the gates have a pull-up and a pull-down network (i.e. we consider FCMOS gates); (c) any transistor in one of such networks is independently controllable.

We will proceed by first considering the two bridged gates and then we will consider the problems related to the logic threshold of fan-out gates (this latter problem exists only for FCMOS gates more complex than NAND and NOR gates).

Let g _x and g _y be the gates whose outputs are bridged and let g be the fan-out gate of g _x that propagates fault effects. All the gates in the fan-out of g _x and g _y , but g, are supposed to be characterized by circuit parameters or input values which do not let fault effects to propagate. This hypothesis allows to focus only on g _x , g _y and g. To detect the fault, the value driven by g _y must prevail over that driven by g _x .

Accordingly to the hypothesis of prime test, the gate g _y is supposed to present an input configuration turning ON all its transistors in the pull-up (down) network. In fact, if t does not detect the fault, any different test turning OFF one of such devices cannot detect the fault. Let R _y (t) be the output resistance of g _y when t is applied.

If t is prime, the ON network (pull-down (up)) of g _x is composed of a series of ON transistors. In fact, any input configuration turning ON ore or more devices in parallel with one or more devices of such a series, will increase the output conductance of g _x . If one of these latter tests detect the fault, then the prime test will also detect it. Therefore, these input configurations are not prime. The set of ON transistors of the ON network of g _x will be denoted as M _x (t).

In Fig. 15, the pull-down of g _y is ON, while the series of M ₀ and M ₁ in g _x is turned ON by the test t indicated in the figure (M _x (t) = {M ₀,M ₁}.

Fig. 15

Example of bridging fault

The resistance of such a series is $R_x(t)=\sum_{i\in M_x(t)} R_i$ (where R _i is the resistance of the i-th device of M _x (t)). To simplify, we can suppose that the bridging resistance is 0 and that the logic threshold of g is at half of the logic swing³. With such an hypothesis, the fault is detectable if:

$$ R_x(t)>R_y \ . \label{e1} $$

(1)

Let us now consider another prime test (q) which presents the same input configuration for g _y and g. Let M _x (q) be the series of transistors turned ON by q. These devices may include a fraction of the transistors in M _x (t) (case a) or not (case b).

In case (b), it is sufficient to set the parameters of the transistors belonging to M _x (q) to values resulting in R _x (q) < R _y . In this way, in fact, q will not detect the fault.

In case (a), instead, let R ⁰ be the resistance of the series of devices in M _x (t) ∩ M _x (q), and let R ¹ be the resistance of the series of devices in M _x (q) − M _x (t). Then, $R_x(q)=R^0+R^1$. In order to detect the fault, it should be:

$$ R^0+R^1>R_y \label{e2} $$

(2)

by subtracting the two inequalities (1) and (2), we have:

$$ R_x(t)-R^0-R^1>0 \ . \label{e3} $$

(3)

In Eq. 3 $R_x(t)-R^0=R^2$ is the resistance of the devices turned ON by t, but not by q. Therefore, q does not detect the fault if R ² < R ¹. It is rather evident that a configuration of device parameters can be selected satisfying such a relationship (we have simply to select a parameters’ configuration increasing the equivalent resistance of devices in M _x (q) − M _x (t)).

In the example of Fig. 15, let q be $\langle ab\!c \rangle = 100$. In this case, M _x (q) = {M ₀,M ₂}, M _x (q) − M _x (t) = {M ₂}, R ¹ is the equivalent resistance of M ₂ and R ² is the equivalent resistance of M ₁.

The same considerations can be repeated for any other prime (with respect to g) test that turns ON the same network of g but is different from t. Configurations of circuit parameters exist that may invalidate any prime test that propagates fault effects from gates different from g. Therefore, we have showed that configurations of circuit parameters exist that can be detected only by t, which is essential.

The input configuration of g, instead, is restricted to those values ensuring the logic observability of x. In case of NAND/NOR CMOS gates, this define the state of the gate and no further consideration has to be made.

In the case of more complex gates (such as AOI and OAI ones), primality imposes that the voltage difference between the fault-free value of x and the logic threshold of g should be minimized. In fact, if the fault is detected by an input configuration changing the logic threshold of g in a direction increasing such a difference, it will be also detected by the considered test.

This implies that the network of g which is ON when x has the fault-free value should connect the output of g to its voltage source through a series of ON transistors including the device driven by x. that, in the faulty circuit, is considered to be partially ON. In fact, any test turning ON an additional device in parallel with such a series would increase the difference between the fault-free voltage of x and the logic threshold. Therefore, if it detect the fault also t will detect it.

The configuration of the inputs which are not assigned in the previous step should maximize the conductance of the complementary network of g ( the one which is OFF under fault-free conditions). In fact, a test that does not satisfy this constraint will be non-prime because the difference between the fault-free value of x and the logic threshold of g will not be minimized.

In the example of Fig. 15, the fault-free ON network of g is the series of M ₁₄ and M ₁₆ which is univocally assigned by observability constraints that impose f = 1. In order to ensure observability, the values of the signals g and h should simply satisfy the boolean condition gh = 0. In this context, they have to be set in order to minimize the difference between the fault-free value (1) of x and the logic threshold of g. This condition can be satisfied by making its pull-up more conductive by turning ON both M ₁₀ and M ₁₁ ($\langle g, h \rangle = 00$).

Let us now consider another prime test q which has the same input configuration for g _x , g _y , but g. Such a test will be characterized by a different series of ON transistors in the fault-free ON network. In fact, the condition imposing to maximize the conductance of the complementary network prevents any prime test to have the same series of ON transistors. As a consequence, also the complementary network will present a different set of ON transistors.

The evaluation of the logic threshold is more complex than the evaluation of the faulty output voltage of the bridged gates. The considerations made in this latter case, however, can be repeated in a qualitative way.

Both t and q feature different series of ON transistors in g. Independently of the complementary network of g, a configuration of IC’s parameters can be individuated that makes the network ON with q more resistive than the network that is ON when t is applied.

Therefore, since this will lead to a larger difference between the logic threshold and the fault-free value, a parameters configuration exists which can be detected only by t.