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Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

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Abstract

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA

    Mihir R. Choudhury & Kartik Mohanram

  2. Baker Hughes Inc., Houston, TX, USA

    Quming Zhou

Authors
  1. Mihir R. Choudhury
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  2. Quming Zhou
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  3. Kartik Mohanram
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Corresponding author

Correspondence to Kartik Mohanram.

Additional information

Responsible Editor: S. Hellebrand

This research was supported by the National Science Foundation CAREER Award CCF-0746850.

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Choudhury, M.R., Zhou, Q. & Mohanram, K. Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J Electron Test 25, 197–207 (2009). https://doi.org/10.1007/s10836-009-5103-9

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  • DOI: https://doi.org/10.1007/s10836-009-5103-9

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