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PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams

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Abstract

This paper proposes a novel method for the simulation-based checking of assertions written in the PSL language. The method uses a system representation model called High-Level Decision Diagrams (HLDDs). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in Property Specification Language (PSL). Other contributions of the paper are a methodology for direct conversion of PSL properties to HLDD and modification of the HLDD-based simulator for assertion checking support. Experimental results show the feasibility and efficiency of the proposed approach.

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Acknowledgments

The work has been supported by European Commission Framework Program projects FP6 VERTIGO and FP7 CREDES, by European Union through the European Regional Development Fund, by Estonian Science Foundation grants 7068 and 7483, Enterprise Estonia funded ELIKO Development Center and Estonian Information Technology Foundation (EITSA).

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Authors and Affiliations

  1. Department of Computer Engineering, Tallinn University of Technology, Raja 15, Tallinn, 12618, Estonia

    Maksim Jenihhin, Jaan Raik, Anton Chepurov & Raimund Ubar

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  1. Maksim Jenihhin
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  2. Jaan Raik
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  3. Anton Chepurov
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  4. Raimund Ubar
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Correspondence to Maksim Jenihhin.

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Responsible Editor: C. Metra

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Jenihhin, M., Raik, J., Chepurov, A. et al. PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J Electron Test 25, 289–300 (2009). https://doi.org/10.1007/s10836-009-5116-4

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  • DOI: https://doi.org/10.1007/s10836-009-5116-4

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