Skip to main content
SpringerLink
Log in

Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often takes a long time—in the order of hundreds of milliseconds or even minutes. As testing such devices would require completion of the calibration process first, lengthy calibration would result in unacceptably long testing time. In this paper, we propose techniques to reduce the calibration time in a production testing environment, thereby reduce the overall testing time for the digitally-calibrated designs. In particular, we propose DfT modifications to accelerate the underlying adaptation algorithms and to terminate the calibration process as soon as it reaches convergence. We discuss the applicability of our techniques to general digitally-calibrated designs and illustrate the details using a case study of a digitally-calibrated pipelined ADC. Simulation results show that, for the target ADC, the proposed technique can achieve, on average, 99.5% reduction in the calibration time, which, in turn, results in a 75% reduction in production test time assuming a typical 300-millisecond testing time for testing the specifications of a calibrated ADC.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Notes

  1. The singularity problem states that, if a calibration stimulus is confined within a small region of a circuit’s input range, it may only activate a small portion of the circuit’s non-idealities. This will cause the adaptation algorithm to converge to a local optimum, which could be far away from the desired global optimum solution.

  2. The effect of noise enhancement can be seen from Fig. 8. During the calibration process, the quantization error q is multiplied by a tap coefficient τ q that effectively amplifies the quantization noise. To compensate for the increased noise, additional sub-ADCs should be added to provide finer resolution. The last few LSBs may be discarded as the final output.

References

  1. Chang H-M, Cheng K-T (2009) TAC: Testing time reduction for digitally-calibrated designs. In: Proc. of 15th IEEE international mixed-signals, sensors, and systems test workshop (IMS3TW), June 2009

  2. Chang H-M, Lin M-S, Cheng K-T (2008) Digitally-assisted analog/RF testing for mixed-signal SoCs. In: Proc of Asian Test Symp (ATS), Nov. 2008

  3. Chang H-M, Chen C-H, Lin K-Y, Cheng K-T (2009) Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC. In: Proc of VLSI Test Symp (VTS), May 2009

  4. Chang H-M, Lin K-Y, Chen C-H, Cheng K-T (2009) A built-in self calibration scheme for pipelined ADCs. In: Proc of 10th Intl Symp Of Quality Electronics Design (ISQED), March 2009

  5. Chiu Y (2008) Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters. In: Proc of 9th IEEE international conference on solid-state and integrated-circuit technology (ICSICT’08), Beijing, 2008

  6. Chiu Y, Tsang CW, Nikolic B, Gray PR (2004) Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Trans Circuits Syst—I. Regular papers 51(1), January 2004

  7. Defrêne K, Boos Z, Weigel R (2008) Digital adaptive IIP2 calibration scheme for CMOS downconversion mixers. IEEE J Solid-State Circuits 43(11):2434–2445

    Article  Google Scholar 

  8. Deng J, Gudem PS, Larson LE, Kimball DF, Asbeck PM (2006) A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications. IEEE J Solid-State Circuits (JSSC) 41(5):1210–1221

    Article  Google Scholar 

  9. Der L, Razavi B (2003) A 2-GHz CMOS image-reject receiver with LMS calibration. IEEE J Solid-State Circuits 38(2):167–175

    Article  Google Scholar 

  10. Harris RW, Chabries DM, Bishop FA (1986) A variable step (VS) adaptive algorithm. IEEE Trans Acoustics, Speech, and Signal Process ASSP-34(2), April 1986

  11. Haykin S (2001) Adaptive filter theory, 4th edn. Prentice-Hall, NJ

    Google Scholar 

  12. Huang J-L, Ong C-K, Cheng K-T (2000) A BIST scheme for On-Chip ADC and DAC testing. In: Proc of design, automation and test in Europe (DATE), April 2000

  13. Kim B, Fu Z, Abraham JA (2007) Transformer-coupled loopback test for differential mixed-signal specifications. In: Proc of VLSI Test Symp (VTS), May 2007

  14. Kwong RH, Johnson EW (1992) A variable step size LMS algorithm. IEEE Trans Signal Process (40)7, July 1992

  15. Liu H-C, Lee Z-M, Wu J-T (2005) A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J Solid-State Circuits 40(5):1047–1056

    Article  Google Scholar 

  16. Liu W, Chang Y, Hsien S-K, Chen B-W, Lee Y-P, Chen W-T, Yang T-Y, Ma G-K, Chiu Y (2009) A 600MS/s 30 mW 0.13 um CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization. In: IEEE international solid-state circuits conference, (ISSCC), San Francisco

  17. Murmann B, Boser BE (2003) A 12-bit 75-MS/s pipelined ADC using open-Loop residue amplification. IEEE J Solid-State Circuits 38(12):2040–2050

    Article  Google Scholar 

  18. Park J, Shin H, Abraham JA (2008) Parallel loopback test of mixed-signal circuits. In: Proc of VLSI Test Symp (VTS), May 2008

  19. Staszewski RB, Wallberg J, Hung C-H, Feygin G, Entezari M, Leipold D (2006) LMS-based calibration of an RF digitally controlled oscillator for mobile phones. IEEE Trans Circuits and Systems—II Express Briefs 53(3):225–229

    Article  Google Scholar 

  20. Tsang C, Chiu Y, Vanderhaegen J, Hoyos S, Chen C, Brodersen R, Nikolić B (2008) Background ADC calibration in digital domain. In: Proc IEEE custom integrated circuits conference (CICC), pp 301–304, Sept. 2008

  21. Variyam PN, Cherubal S, Chatterjee A (2002) Prediction of analog performance parameters using fast transient testing. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(3), March 2002

  22. Voorakaranam R, Akbay SS, Bhattacharya S, Cherubal S, Chatterjee A (2007) Signature testing of analog and RF circuits: algorithms and methodology. IEEE Trans Circuits and Systems—I: Regular Paper 54(5), May 2007

  23. Wang X, Hurst PJ, Lewis SH (2004) A 12-Bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J of Solid-State Circuits 39(11), Nov. 2004

  24. Wang P-Y, Zhan J-H, Chang H-H, Hsieh B-Y (2008) An analog enhanced all digital RF fractional-N PLL with self-calibrated capability. In: Proc IEEE custom integrated circuits conference (CICC), pp 749–752, Sept. 2008

  25. Xing H, Jiang H, Chen D, Geiger R (2007) A fully digital-compatible BIST strategy for ADC linearity testing. In: Proc of IEEE international test conference (ITC)

Download references

Acknowledgements

This work is partially supported by the Gigascale Systems Research Center (GSRC), one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program.

Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, University of California, Santa Barbara, CA, 93111, USA

    Hsiu-Ming Sherman Chang & Kwang-Ting Tim Cheng

  2. SoC Technology Center, Industrial Technology Research Institute, HsinChu, Taiwan

    Kuan-Yu Lin

Authors
  1. Hsiu-Ming Sherman Chang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kuan-Yu Lin
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kwang-Ting Tim Cheng
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Hsiu-Ming Sherman Chang.

Additional information

Responsible Editor: K. Arabi

Preliminary versions of this paper have been presented in the 27th IEEE VLSI Test Symposium [1] and the 15th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop [3].

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chang, HM.S., Lin, KY. & Cheng, KT.T. Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study. J Electron Test 26, 59–71 (2010). https://doi.org/10.1007/s10836-009-5123-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-009-5123-5

Keywords

Search

Navigation