Abstract
This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been used in the past for lower-speed (i.e. ≤12.8 Gbps) applications. However, success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost (off-the-shelf) components are used so that the method can be applied to test scenarios requiring many high-speed channels. Analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method. A Development Platform is also described that facilitates individual module characterization and integration of multiple modules to form customized test systems.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Cardakli MC, Willner AE (2002) Synchronization of a network element for optical packet switching using optical correlators and wavelength shifting. IEEE Photon Technol Lett 14:1375–1378
Evans AC (2007) The new ATE: protocol aware. Proc of the IEEE International Test Conference (ITC’07)
Fritzsche WA, Haque AE (2008) Low cost testing of multi-GBit device pins with ATE assisted loopback instrument. Proc of the IEEE Intl Test Conf (ITC’08), Paper 4.2, Santa Clara
Gray CE, Liboiron-Ladouceur O, Keezer DC, Bergman K (2007) Co-development of test electronics and PCI express interface for a multi-Gbps optical switching network. Proc of the IEEE Intl Test Conf (ITC’07), Paper 22.1, Santa Clara, California
Keezer DC, Minier D, Ducharme P, Viens D, Flynn G, McKillop JS (2007) Multi-GHz loopback testing using MEMs switches and SiGe logic. Proc of the IEEE Intl Test Conf (ITC’07), paper 8.1, Santa Clara, California, Oct. 2007
Keezer DC, Minier D, Ducharme P, Majid A (2008) An electronic module for 12.8 Gbps multiplexing and loopback test. Proc of the IEEE Intl Test Conf (ITC’08), Paper 27.3, Santa Clara, California, October 2008
Keezer DC, Gray C, Majid A, Minier D, Ducharme P (2009) A development platform and electronic modules for automated test up to 20 Gbps. Proc of the IEEE Intl Test Conf (ITC'09), Paper 14.3, Austin, Texas, November 2009
Kodi AK, Louri A (2005) Design of a high-speed optical interconnect for scalable shared-memory multiprocessors. IEEE Micro 25:41–49
Liboiron-Ladouceur O, Gray C, Keezer DC, Bergman K (2006) Bit-parallel message exchange and data recovery in optical packet switched interconnection networks. Photon Tech Lett
Moreira J et al (2008) Beyond 10 Gbps? Challenges of characterizing future I/0 interfaces with automated test equipment. Proc of the IEEE Intl Test Conf (ITC’08), Lecture 2.3, Santa Clara
Acknowledgments
This work was conducted as a joint R&D project between Georgia Tech and IBM Canada. System level tests were performed at both the Georgia Tech and IBM, Bromont facilities.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: Karim Arabi
This paper is the expanded version of the paper entitled as “Demonstration of 20 Gbps Digital Test Signal synthesis Using SiGe and InP Logic” which was presented at the International Mixed-Signal, Sensors, and Systems Test Workshop (IMS3TW 09), Scottsdale, Arizona, June, 2009.
Rights and permissions
About this article
Cite this article
Keezer, D., Gray, C., Minier, D. et al. Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic. J Electron Test 26, 87–96 (2010). https://doi.org/10.1007/s10836-009-5124-4
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-009-5124-4