Skip to main content
Log in

Test Data Compression Using Multi-dimensional Pattern Run-length Codes

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Test data compression is an efficient methodology in reducing large test data volume for system-on-a-chip designs. In this paper, a variable-to-variable length compression method based on encoding runs of compatible patterns is presented. Test data in the test set is divided into a number of sequences. Each sequence is constituted by a series of compatible patterns in which information such as pattern length and number of pattern runs is encoded. Theoretical analyses on the evolution of the proposed Multi-Dimensional Pattern Run-Length Compression (MD-PRC) are made respectively from one-Dimensional-PRC to three-Dimensional-PRC. To demonstrate the effectiveness of the proposed method, experiments are conducted on both larger ISCAS’89 benchmarks and the industrial circuits with large number of don’t cares. Results show this method can achieve significant compression in test data volume and have good adaptation to industrial-size circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. Chandra A, Chakrabarty K (2001) System-on-a-chip data compression and decompression architecture based on Golomb codes. IEEE Trans Computer-Aided Design Integr Circuits Syst 20(3):355–368

    Article  Google Scholar 

  2. Chandra A, Chakrabarty K (2003) A unified approach to reduce SoC test data volume, scan power and testing time. IEEE Trans Computer-Aided Design Integr Circuits Syst 22(3):352–363

    Article  Google Scholar 

  3. Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Comput 52(8):1076–1088

    Article  Google Scholar 

  4. El-Maleh AH (2008) Effcient test compression technique based on block merging. IET Comput Digit Tech 2(5):327–335

    Article  Google Scholar 

  5. El-Maleh AH, Al-Abaji RH (2002) Extended frequency-directed run length code with improved application to system-on-a-chip test data compression. In Proc 9th IEEE int conf electronics, circuits and systems, pp 449–452

  6. Gonciari PT, Al-Hashimi B, Nicolici N (2002) Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression. In Proc design automation test in Europe, Paris, pp 604–611

  7. Hamzaoglu I, Patel JH (2000) Test set compaction algorithms for combinational circuits. IEEE Trans Computer-Aided Design Integr Circuits Syst 19(8):957–963

    Article  Google Scholar 

  8. Huffman DA (1952) A Method for the construction of minimum redundancy codes. In Proc IRE 40:1098–1101

    Article  Google Scholar 

  9. Jas A, Ghosh-Dastidar J, Ng M-E, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Computer-Aided Design Integr Circuits Syst 22(6):797–806

    Article  Google Scholar 

  10. Kavousianos X, Kalligeros E, Nikolos D (2007) Optimal selective Huffman coding for test-data compression. IEEE Trans Comput 56(8):1146–1152

    Article  MathSciNet  Google Scholar 

  11. Koenemann B, Banhart C, Keller B, Snethen T, Farnsworth O, Wheater D (2001) A SmartBIST variant with guaranteed encoding. In Proc Asia test symp, pp 325–330

  12. Mitra S, Kim KS (2003) XMAX: X-Tolerant architecture for maximal test compression. In Proc IEEE int conf computer design, pp 326–330

  13. Mitra S, Kim KS (2004) X-Compact: an efficient response compaction technique. IEEE Trans Computer-Aided Design Integr Circuits Syst 23:421–432

    Article  Google Scholar 

  14. Nourani M, Tehranipour M (2005) RL-Huffman encoding for test compression and power reduction in scan application. ACM Trans Des Autom Electron Syst (TODAES) 10(1):91–115

    Article  Google Scholar 

  15. Rajski J, Tyszer J, Kassab M, Mukherjee N (2004) Embedded deterministic test. IEEE Trans Computer-Aided Design Integr Circuits Syst 23:776–792

    Article  Google Scholar 

  16. Ruan X, Katti R (2006) An efficient data-independent technique for compressing test vectors in systems-on-a-chip. In: proc IEEE emerging VLSI technologies and architecture symp, pp 153-158

  17. Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303

    Article  Google Scholar 

  18. Tehranipoor M, Nourani M, Chakrabarty K (2005) Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans VLSI Syst 13(6):719–731

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Wang-Dauh Tseng.

Additional information

Responsible Editor: N. A Touba

Rights and permissions

Reprints and permissions

About this article

Cite this article

Tseng, WD., Lee, LJ. Test Data Compression Using Multi-dimensional Pattern Run-length Codes. J Electron Test 26, 393–400 (2010). https://doi.org/10.1007/s10836-009-5138-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-009-5138-y

Keywords

Navigation