Abstract
Today’s high performance computer systems must have fast, reliable access to memory and I/O devices. Unfortunately, inter-symbol interference, transmission line effects and other noise sources can distort data transfers. Engineers must therefore determine if bus designs have signal integrity—i.e., can transfer data with minimal amplitude or timing distortion. One method of determining signal integrity on buses is to conduct a set of data transfers and measure various signal parameters at the receiver end. But the tests must be conducted with stressful test patterns that maximize noise to help identify any potential problems. In this paper we describe how an evolutionary algorithm was used to evolve test patterns for use in intrinsic testing.
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Notes
1 GT/s = 1 giga-transfer/s. A 100 MHz FSB performing 4 transfers per cycle has a 0.4 GT/s transfer rate. With a 64-bit wide FSB, 0.4 GT/s is equivalent to a 3.2 GByte/s bandwidth.
Under normal operating conditions V ref = V nom. We only move V ref away from V nom to determine the voltage margin.
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Falconer, M., Greenwood, G., Morgan, K. et al. Using Evolutionary Algorithms for Signal Integrity Assessment of High-Speed Data Buses. J Electron Test 26, 297–305 (2010). https://doi.org/10.1007/s10836-010-5141-3
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DOI: https://doi.org/10.1007/s10836-010-5141-3