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Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

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Abstract

This paper introduces an approach to effectively exploit incremental SAT in order to search for multiple equivalence-preserving transformations of combinational circuits. Typical applications, such as redundancy removal with observability and external care conditions, adequate abstractions and other optimizations used in a state-of-the-art SAT-based model checker, can reap benefits from the proposed strategies. Our techniques exploit SAT incrementality, by iteratively refining the set of candidate transformations with a counter-example driven analysis, until an unsatisfiable point is reached. The key point of our technique is the ability to address satisfiable instances first, where SAT solvers are generally much faster than with unsatisfiable runs. We also discuss partitioning and problem reduction issues, that are fundamental in order to provide a scalable approach. Experimental results show the effectiveness of the proposed strategies.

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Notes

  1. Without loss of generality, here we limit the discussion to single output gates.

References

  1. Baumgartner J, Mony H, Aziz A (2008) Optimal constraint-preserving netlist simplification. In: Proc formal methods in computer-aided design

  2. Berry G, Shiple TR, Touati H (1996) Constructive analysis of cyclic circuits. In: IDTC’96: international design and testing conference, Paris, France

    Google Scholar 

  3. Biere A, Jussila T (2008) The model checking competition web page. http://fmv.jku.at/hwmcc08

  4. Bjesse P, Claessen K (2000) SAT-based verification without state space traversal. In: Proc formal methods in computer-aided design. LNCS, vol 1954. Springer, Austin

    Chapter  Google Scholar 

  5. Bouali A, Bres Y, Berry G, Sentovich EM (2002) State abstraction techniques for the verification of synchronous circuits. In: dcc02: designing correct circuits 2002. Grenoble, France

    Google Scholar 

  6. Cabodi G, Camurati P, Garcia L, Murciano M, Nocco S, Quer S (2008) Trading-off SAT search and variable quantifications for effective unbounded model checking. In: Proc. formal methods in computer-aided design. Portland, Oregon, pp 205–212

    Google Scholar 

  7. Cabodi G, Camurati P, Murciano M (2008) Automated abstraction by incremental refinement in interpolant-based model checking. In: Proc int’l conf on computer-aided design. ACM, San Jose, pp 129–136

    Google Scholar 

  8. Cabodi G, Crivellari M, Nocco S, Quer S (2005) Circuit based quantification: back to state set manipulation within unbounded model checking. In: Proc design automation & test in Europe conf., IEEE Computer Society, Munich

    Google Scholar 

  9. Cabodi G, Dipietro L, Murciano M, Nocco S (2009) Exploiting incrementality in sat-based search for multiple equivalence-preserving transformations in combinational circuits. In: Proceedings of the 2009 IEEE international high level design validation and test workshop. IEEE Computer Society

  10. Cabodi G, Murciano M, Nocco S, Quer S (2006) Stepping forward with interpolants in unbounded model checking. In: Proc int’l conf on computer-aided design. ACM, San Jose, pp 772–778

    Google Scholar 

  11. Cabodi G, Murciano M, Nocco S, Quer S (2008) Boosting interpolation with dynamic localized abstraction and redundancy removal. ACM Trans Des Automat Electron Syst 13(1):309–340

    Google Scholar 

  12. Chang SC, Cheng DI, Yeh CW (1998) On removing multiple redundancies in combinational circuits. In: Proc design automation & test in Europe conf, pp 738–742

  13. Chang SC, Marek-Sadowska M (1996) Perturb and simplify: optimizing combinational circuits with external don’t cares. In: Proc European design and test conference, pp 402–406

  14. Chatterjee M, Pradhan DK, Kunz W (1998) LOT: logic optimization with testability—new transformations for logic synthesis. IEEE Trans Comput-Aided Des 17(5):386–398

    Article  Google Scholar 

  15. Chen G, Reddy SM, Pomeranz I, Rajski J (2006) New procedures to identify redundant stuck-at faults and removal of redundant logic. In: Proc int conf on VLSI, pp 419–424

  16. Cooper KD, Harvey TJ, Kennedy K (2001) A simple, fast dominance algorithm. Software Pract Ex 4:1–10

    Google Scholar 

  17. Eén N, Sörensson N (2003) Temporal induction by incremental sat solving. Electron Notes Theor Comp Sci 89(4):543–560

    Article  Google Scholar 

  18. Eén N, S\(\ddot{\mbox{o}}\)rensson N (2009) The minisat SAT solver. http://minisat.se

  19. Fraer R, Ikram S, Kamhi G, Leonard T, Mokkedem A (2002) Accelerated verification of RTL assertions based on satisfiability solvers. In: Proc HLDVT

  20. Gault JW, Robinson JP, Reddy SM (1972) Multiple fault detection in combinational networks. IEEE Trans Comput C-21(1):31–36

    Article  MATH  MathSciNet  Google Scholar 

  21. Khasidashvili Z, Hanna Z (2003) Sat-based methods for sequential hardware equivalence verification without synchronization. In: BMC’03: first international workshop on bounded model checking. Boulder, Colorado, pp 593–607

    Google Scholar 

  22. Kim J, Marques-Silva J, Savoj H, Sakallah KA (1997) RID-GRASP: redundancy identification and removal using GRASP. In: Proc int’l workshop on logic synthesis

  23. Kunz W (1993) HANNIBAL: an efficient tool for logic verification based on recursive learning. In: Proc int’l conf on computer-aided design

  24. Kunz W, Menon PR (1994) Multi-level logic optimization by implication analysis. In: Proc int’l conf on computer-aided design, pp 6–13

  25. Malik S (1994) Analysis of cyclic combinational circuits. IEEE Trans Comput-Aided Des 13:950–956

    Article  Google Scholar 

  26. Marques-Silva JP, Sakalla KA (1996) GRASP—a new search algorithm for satisfiability. In: Int’l conference on tool with artificial intelligence

  27. McMillan KL (2005) Don’t-care computation using k-clause approximation. In: Proc int’l workshop on logic synthesis

  28. Millán ES, Entrena LA, Espejo JA (2008) Logic transformations by multiple wire network addition. In: Proc EUROMICRO conf on digital system design architectures, methods and tools, pp 779–786

  29. Mishchenko A (2005) ABC: a system for sequential synthesis and verification. http://www.eecs.berkeley.edu/~alanmi/abc/

  30. Mishchenko A, Brayton RK (2005) SAT-based complete don’t-care computation for network optimization. In: Proc design automation & test in Europe conf, pp 412–417

  31. Mony H, Baumgartner J, Aziz A (2005) Exploiting constraints in transformation-based verification. In: Borrione D, Paul W (eds) Proc. correct hardware design and verification methods. LNCS, vol 3275. Springer, Edimburgh, pp 269–284

    Chapter  Google Scholar 

  32. Pomeranz I, Reddy SM (1996) On finding functionally identical and functionally opposite lines in combinational logic circuits. In: Proc int conf on VLSI, pp 254–259

  33. Saldanha A, Wang AR, Brayton RK, Sangiovanni-Vincentelli AL (1989) Multi-level logic simplification using don’t cares and filters. In: Proc design automation conf, pp 277–282

  34. Saluja N, Khatri SP (2004) A robust algorithm for approximate compatible observability don’t care computation. In: Proc design automation conf, pp 422–427

  35. Savoj H, Brayton RK (1990) The use of observability and external don’t cares for the simplification of multi-level networks. In: Proc design automation conf, pp 297–301

  36. Sinz C (2005) Towards an optimal CNF encoding of boolean cardinality constraints. In: Proc principles and practice of constraint programming, pp 827–831

  37. Veneris A, Abadir MS, Amiri M (2002) Design rewiring using ATPG. In: Proc int’l test conf, pp 223–232

  38. Zhu Q, Kitchen N, Kuehlmann A, Sangiovanni-Vincentelli A (2006) SAT sweeping with local observability don’t-cares. In: Proc design automation conf, pp 229–234

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Authors and Affiliations

  1. Politecnico di Torino, C.so Duca degli Abruzzi, 24, 10129, Turin, Italy

    Gianpiero Cabodi, Leandro Dipietro, Marco Murciano & Sergio Nocco

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  1. Gianpiero Cabodi
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  2. Leandro Dipietro
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  3. Marco Murciano
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  4. Sergio Nocco
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Correspondence to Marco Murciano.

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Responsible Editor: P. Mishra

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Cabodi, G., Dipietro, L., Murciano, M. et al. Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT . J Electron Test 26, 261–278 (2010). https://doi.org/10.1007/s10836-010-5144-0

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