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Efficient Concurrent Self-Test with Partially Specified Patterns

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Abstract

Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation in the system. This paper improves existing techniques for concurrent BIST that are based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test length and fault detection latency, which allows to frequently test critical faults. As a consequence, the likelihood of fault accumulation is reduced. Experiments with benchmark circuits show that the hardware overhead is significantly lower than the overhead of the state of the art. Moreover, a case-study on a super-scalar RISC processor demonstrates the feasibility of the method.

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Acknowledgment

This work has been supported by the Deutsche Forschungsgesellschaft (DFG) under grants Wu245/3-3 and Wu245/5-2.

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  1. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, 70569, Stuttgart, Germany

    Michael A. Kochte, Christian G. Zoellin & Hans-Joachim Wunderlich

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  1. Michael A. Kochte
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  2. Christian G. Zoellin
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  3. Hans-Joachim Wunderlich
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Correspondence to Michael A. Kochte.

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Responsible Editor: C. Metra

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Kochte, M.A., Zoellin, C.G. & Wunderlich, HJ. Efficient Concurrent Self-Test with Partially Specified Patterns. J Electron Test 26, 581–594 (2010). https://doi.org/10.1007/s10836-010-5167-6

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