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Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip

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Abstract

Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips since most mainstream memories use a source-synchronous interface. This paper presents a new Skew Measurement and Compensation Module (SMCM) design for off-chip skew calibration from Time Domain Reflectometry (TDR) measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution. Circuit complexity is reduced through use of the proposed automatic edge detection method which controls coarse/fine operations. We also present skew compensation circuits which can de-skew off-chip signals based on the skew calibration. The SMCM occupies a small area, making it suitable for implementation in a Built-Off Test (BOT) chip. The circuits were implemented using a 130 nm technology in a Built-Off Test Interface (BOTI) developed for 800 Mbps DDR2 memory functional test.

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References

  1. Akbay SS, Halder A, Chatterjee A, Keezer D (2004) Low-cost test of eembedded RF/analog/mixed-signal circuits in SOPs. IEEE Trans Adv Packaging 27(2):352–363

    Article  Google Scholar 

  2. Choy CS, Ku MH, Chan CF (1997) A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. IEEE J Solid-state Circuits 32(6):913–917

    Article  Google Scholar 

  3. Chun S, Swaminathan M, Smith LD, Srinivasan J, Jin Z, Iyer MK (2001) Modeling of simultaneous switching noise in high speed systems. IEEE Trans Adv Packaging 24(2):132–142

    Article  Google Scholar 

  4. Dudek P, Szczepanski S, Hatfield JV (2000) A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE J Solid-state Circuits 35(2):240–247

    Article  Google Scholar 

  5. Jansson JP, Manttyniemi A, Kostamovaara J (2006) A CMOS time-to-digital converter with better than 10ps single-shot precision. IEEE J Solid-state Circuits 41(6):1286–1296

    Article  Google Scholar 

  6. Keezer DC, Minier D, Caron MC (2003) A production-oriented multiplexing system for testing above 2.5 Gbps. In: International test conference, pp 191–200

  7. Keezer DC, Minier D, Caron M-C (2004) Multiplexing ATE channels for production testing at 2.5 Gbps. In: IEEE design and test of computers, pp 288–301

  8. Levine PM, Roberts GW (2004) A high-resolution flash time-to-digital converter and calibration scheme. In: International test conference, pp 1148–1157

  9. Lim JH, HA JC, Jung WY, Kim YJ, Wee JK (2007) A novel high speed and low voltage CMOS level-up/down shifter design for multiple-power and multiple-clock domain chips. IEICE Trans Electron E90-C(3):644–648

    Article  Google Scholar 

  10. Nelms M, Gorman K, Anand D (2004) Generating at-speed array fail maps with low-speed ATE. In: VLSI test symposium, pp 87–92

  11. Restle PJ, Deutsch A (1998) Designing the best clock distribution network. In: IEEE symposium on VLSI circuits digest of technical papers, pp 2–5

  12. Senthinathan R, Prince JL (1993) Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise. IEEE J Solid-state Circuits 28(12):1383–1388

    Article  Google Scholar 

  13. Shimanouchi M (2004) Timing accuracy enhancement by a new calibration scheme for multi- Gbps ATE. In: International test conference, pp 567–576

  14. Sunter S, Roy A (2007) A self-testing BOST for high-frequency PLLs, DLLs, and SerDes. In: International test conference, paper 4.3

  15. Uyttenhove K, Marques A, Steyaert M (2000) A 6-bit 1 GHz aquisition speed CMOS flash ADC with digital error correction. In: IEEE custom integrated circuit conference, pp 249–252

  16. Uyttenhove K, Steyaert M (2003) A 1.8-V 6-bit 1.3 GHz flash ADC in 0.25-\(\upmu\)m CMOS. IEEE J Solid-state Circuits 38(7):1115–1122

    Article  Google Scholar 

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Correspondence to Kihyuk Han.

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Responsible Editor: C. Metra

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Han, K., Park, J., Lee, J.W. et al. Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. J Electron Test 27, 429–439 (2011). https://doi.org/10.1007/s10836-011-5213-z

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  • DOI: https://doi.org/10.1007/s10836-011-5213-z

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