Skip to main content
SpringerLink
Log in

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

Abbreviations

ADC:

Analog to digital converter

ATE:

Automated test equipment

BI:

Burn-in

BICS:

Built-in current sensor

BIST:

Built-in self test

CUT:

Circuit under test

DBT:

Defect based testing

DfT:

Design for test

GOS:

Gate oxide short

IDD:

Current test

IDDQ:

Quiescent current test

IDDT:

Transient current test

IDDX:

Dynamic current test

OA:

Operational amplifier

PDF:

Probability density function

SI:

Switched current

SiP:

System in package

SoC:

System on chip

References

  1. Alorda B, Canals V, Segura J (2004) A two-level power-grid model for transient current testing evaluation. J Electron Test 20(5):543–552

    Article  Google Scholar 

  2. Alorda B, de Paul I, Segura J (2007) Charge-based testing BIST for embedded memories. IET Comput Digital Tech 1(5):481–490. doi:10.1049/iet-cdt:20060058

    Article  Google Scholar 

  3. Arumí D, Rodríguez-Montañés R, Figueras J (2008) Experimental characterization of CMOS interconnect open defects. IEEE Trans Comput Aided Des Integr Circuits Syst 27:123–136. doi:10.1109/TCAD.2007.907255

    Article  Google Scholar 

  4. Chen CS, Lo JC, Xia T (2006) An indirect current sensing technique for IDDQ and IDDT tests. ACM Great Lakes Symposium VLSI: 235–240. doi:0.1145/1127908.1127964

  5. Ekekon OK, Maltabas S, Margala M (2010) A new built-in IDDQ testing method using programmable BICS. IEEE Int Symp Circuits Syst: 3545–3548. doi:10.1109/ISCAS.2010.5537811

  6. Hsu CL, Ho MH, Lin CF (2009) Novel built-in current-sensor-based IDDQ testing scheme for CMOS integrated circuits. IEEE Trans Instrum Meas 58(7):2196–2208. doi:10.1109/TIM.2009.2013668

    Article  Google Scholar 

  7. Hughes JB, Moulding KW (1993) S2I: a switched-current technique for high performance. IEE Electron Lett 29(16):1400–1401. doi:10.1049/el:19930938

    Article  Google Scholar 

  8. Kaminska B, Arabi K, Bell I, Goteti P, Huertas JL, Kim B, Rueda A, Soma M (1997) Analog and mixed-signal benchmark circuits—first release. Proc IEEE Int Test Conf 1997:183–190. doi:10.1109/TEST.1997.639612

    Google Scholar 

  9. Lechuga Y, Mozuelos R, Allende MA, Martínez M, Bracho S (2005) Fault detection in switched current circuits using built-in transient current sensors. J Electron Test Theory Appl 21(6):583–598

    Article  Google Scholar 

  10. Lechuga Y, Mozuelos R, Martínez M, Bracho S (2002) Built-in dynamic current sensor for hard to detect faults in mixed signal ICs. Proc Des Autom Test Eur Conf Exhib: 205–211. doi:10.1109/DATE.2002.998271

  11. Lechuga Y, Mozuelos R, Martínez M, Bracho S (2003) Built-in sensor based on current supply high-frequency behaviour. IEE Electron Lett 39(10):775–777. doi:10.1049/el:20030475

    Article  Google Scholar 

  12. Marinissen EJ, Zorian Y (2009) IEEE Std 1500 enables modular SoC testing. IEEE Des Test Comput 26(1):8–17. doi:10.1109/MDT.2009.12

    Article  Google Scholar 

  13. Olbrich T, Perez J, Grout IA, Richardson AMD, Ferrer C (1996) Defect-oriented vs. schematic-level based fault simulation for mixed-signal ICs. Proc IEEE Int Test Conf 1996:511–520. doi:10.1109/TEST.1996.557076

    Google Scholar 

  14. Robson M, Russell G (1996) Current monitoring technique for testing embedded analogue functions in mixed-signal ICs. IEE Electron Lett 32(9):796–798. doi:10.1049/el:19960557

    Article  Google Scholar 

  15. Sabade S, Walker DMH (2004) IDDX-based test methods: a survey. ACM Trans Des Automation Electron Syst 9:159–198

    Article  Google Scholar 

  16. Sachdev M, Janssen P, Zieren V (1998) Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. Proc IEEE Int Test Conf 1998:204–213. doi:10.1109/TEST.1998.743153

    Google Scholar 

  17. Sachdev M, Pineda de Gyvez J (2007) Defect-oriented testing for nano-metric CMOS VLSI circuits. Springer, 2nd Ed

  18. Segura J, Hawkins C (2004) CMOS electronics: how it works, how it fails. IEEE Press, Piscataway

    Book  Google Scholar 

  19. Semiconductor Industry Association (2007) International technology roadmap for semiconductors 2007. ITRS Web. http://www.itrs.net/Links/2007ITRS/Home2007.htm

  20. Siskos S (2010) FGMOS based built-in current sensor for low supply voltage analog and mixed-signal circuits testing. IEEE Comput Soc Annu Symp VLSI: 259–264. doi:10.1109/ISVLSI.2010.31

  21. Tráff H, Holmberg T, Eriksson S (1991) Application of switched-current technique to algorithmic DA and AD converters. Proc IEEE Int Symp Circ Syst 3:1549–1552. doi:10.1109/ISCAS.1991.176672

    Article  Google Scholar 

  22. Yellampalli S, Korivi NS, Marulanda J (2008) Built-in current sensor for quiescent current testing in analog CMOS circuits. 40th Southeastern Symposium on System Theory: 329–333. doi:10.1109/SSST.2008.4480248

Download references

Acknowledgments

This work was funded by the Spanish Comisión Interministerial de Ciencia y Tecnología under the projects TIC-2001-0619 and TEC2007-65588.

Author information

Authors and Affiliations

  1. Microelectronic Engineering Group, Department TEISA, University of Cantabria, Avda, Los Castros sn, 39005, Santander, Spain

    Román Mozuelos, Yolanda Lechuga, Mar Martínez & Salvador Bracho

Authors
  1. Román Mozuelos
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yolanda Lechuga
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mar Martínez
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Salvador Bracho
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Román Mozuelos.

Additional information

Responsible Editor: C. Metra

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mozuelos, R., Lechuga, Y., Martínez, M. et al. Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor. J Electron Test 27, 177–192 (2011). https://doi.org/10.1007/s10836-011-5214-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5214-y

Keywords

Search

Navigation