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A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

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Abstract

Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (IP) core integration into complex system-on-chip (SOC) architectures. These cores require thorough verification of their functionality to avoid erroneous behavior in the final device. Formal verification methods are capable of detecting any design bug. However, due to state explosion, their use remains limited to small circuits. Alternatively, simulation-based verification can explore hardware descriptions of any size, although the corresponding stimulus generation, as well as functional coverage definition, must be carefully planned to guarantee its efficacy. In general, static input space optimization methodologies have shown better efficiency and results than, for instance, Coverage Directed Verification (CDV) techniques, although they act on different facets of the monitored system and are not exclusive. This work presents a constrained-random simulation-based functional verification methodology where, on the basis of the Parameter Domains (PD) formalism, irrelevant and invalid test case scenarios are removed from the input space. To this purpose, a tool to automatically generate PD-based stimuli sources was developed. Additionally, we have developed a second tool to generate functional coverage models that fit exactly to the PD-based input space. Both the input stimuli and coverage model enhancements, resulted in a notable testbench efficiency increase, if compared to testbenches with traditional stimulation and coverage scenarios: 22% simulation time reduction when generating stimuli with our PD-based stimuli sources (still with a conventional coverage model), and 56% simulation time reduction when combining our stimuli sources with their corresponding, automatically generated, coverage models.

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Acknowledgments

This work was partially supported by the São Paulo Research Foundation FAPESP, and by the National Council of Technological and Scientific Development CNPq, both from Brazil.

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Authors and Affiliations

  1. School of Engineering, University of Sao Paulo, Av. Prof. Luciano Gualberto, trav.3 nº.158, 05424-970, Sao Paulo, Brazil

    Carlos Iván Castro Márquez, Edgar Leonardo Romero Tobar, Marius Strum & Wang Jiang Chau

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  1. Carlos Iván Castro Márquez
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  2. Edgar Leonardo Romero Tobar
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  3. Marius Strum
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  4. Wang Jiang Chau
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Corresponding author

Correspondence to Carlos Iván Castro Márquez.

Additional information

A presentation based on this article was made at the Eleventh IEEE Latin-American Test Workshop, Punta del Este, Uruguay, March 28-31, 2010

Responsible Editor: E. Cota

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Castro Márquez, C.I., Romero Tobar, E.L., Strum, M. et al. A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J Electron Test 27, 485–503 (2011). https://doi.org/10.1007/s10836-011-5225-8

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  • DOI: https://doi.org/10.1007/s10836-011-5225-8

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