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An Output Response Analyzer Circuit for ADC Built-in Self-Test

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Abstract

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs’ parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.

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Authors and Affiliations

  1. Department of Electronics Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan

    Hsin-Wen Ting

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  1. Hsin-Wen Ting
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Correspondence to Hsin-Wen Ting.

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Responsible Editor: J. A. Abraham

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Ting, HW. An Output Response Analyzer Circuit for ADC Built-in Self-Test. J Electron Test 27, 455–464 (2011). https://doi.org/10.1007/s10836-011-5235-6

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  • DOI: https://doi.org/10.1007/s10836-011-5235-6

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