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A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect

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An Erratum to this article was published on 06 September 2011

Abstract

FPGA test cost can be reduced effectively by minimizing the number of test configurations. To realize it, a self-configurable structure was proposed before to test the cross-point-based switch box in FPGA. In this paper, a technique of partially self-configurable multiplexers is presented to reduce the test cost of completely multiplexer-based FPGA interconnect cost-efficiently. The additional self-configured structure, called test point here, is only added to the most efficient configuration ports, which is selected through analyzing test configurations, so the test cost can reduce with the minimal area overhead. It is shown that for testing all interconnect stuck-at faults in FPGAs like Virtex-II and Spartan-3 the test configurations can be reduced to 8 with merely about 1.2% area penalty.

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References

  1. Abramovici M, Stroud CE (2001) BIST-based test and diagnosis of FPGA logic blocks. IEEE transactions on VLSI systems 9(1):159–172

    Article  Google Scholar 

  2. Actel inc (2010) ProASIC3 FPGA fabric user’s guide

  3. Actel inc (2009) Actel inc (2009) ProASIC3 Flash Family FPGAs Datasheet, IGLOO Low Power Flash FPGAs Datasheet. http://www.actel.com/documents/PA3_DS.pdf, http://www.actel.com/documents/IGLOO_DS.pdf

  4. Chmelar E (2004) Minimize the number of test configurations for FPGAs. ICCAD, pp 899–902

  5. Dutt S, Verma V, Suthar V (2008) Built-in-self-test of FPGAs with provable diagnosabilities and high diagnostic coverage with application to online testing. IEEE Transactions on Computer-Aided Design of integrated circuits and systems, pp 309-326

  6. Fernandes D, Harris I (2003) Application of built-in self test for interconnect testing of FPGAs. Proceedings IEEE Int. Test Conference, pp 1248–1257

  7. Karp RM (1982) Dynamic programming meets the principle of inclusion and exclusion. Operations Research Letters

  8. Kohn S, Gottlieb A, Kohn M (1997) A Generating Function Approach to the Traveling Salesman Problem, Proceedings of the annual conference

  9. Lemieux G, Lee E, Tom M, Yu A (2004) Directional and single-driver wires in FPGA interconnect. In IEEE International Conference on Field-Programmable Technology, pp 41–48

  10. McCracken S, Zilic Z (2002) FPGA test time reduction through a novel interconnect testing scheme. Proc. ACM Int’l Symp. on Field Programmable Gate Arrays, pp 136–144

  11. Smith J, Xia T, Stroud C (2006) An automated BIST architecture for testing and diagnosing FPGA interconnect faults. J Electron Test Theory Appl 22(3):239–253

    Article  Google Scholar 

  12. SST inc (2010) SPI Serial Flash 25 Series Product Brief, http://ww1.microchip.com/downloads/en/DeviceDoc/01357A.pdf

  13. Stroud C, Wijesuriya S, Hamilton C, M Abramovici (1998) Built-in self-test of FPGA interconnect. Proceedings IEEE Int. Test Conference, pp 404–411

  14. Stroud C, Nall J, Lashinsky M, Abramovici M (2002) BIST-based diagnosis of FPGA interconnect. Proceedings IEEE Int. Test Conference, pp 618–627

  15. Tahoori M, Mitra S (2003) Automatic configuration generation for FPGA interconnect testing. Proc. 21st VLSI Test Symp, pp 134–139

  16. Tahoori M, Mitra S (2005) Application independent testing of FPGA interconnects. IEEE Trans Comput Aided Des Integrated Circ Syst 24(11):1774–1783

    Article  Google Scholar 

  17. Wunderlich HJ (1998) BIST for systems-on-a-chip. INTEGRATION, the VLSI journal

  18. Xilinx inc (2008) Spartan-3 FPGA Family Advanced Configuration Architecture

Download references

Acknowledgments

The authors gratefully acknowledge the support from the SST Inc. and thank Mr. Tsung-lu Syu and Wilson Yee for their valuable discussions.

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Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    Zhu Jianfeng, He Hu, Wu Dong & Pan Liyang

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  1. Zhu Jianfeng
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  2. He Hu
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  3. Wu Dong
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  4. Pan Liyang
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Correspondence to Pan Liyang.

Additional information

Responsible Editor: C. E. Stroud

An erratum to this article can be found at http://dx.doi.org/10.1007/s10836-011-5249-0

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Jianfeng, Z., Hu, H., Dong, W. et al. A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. J Electron Test 27, 647–655 (2011). https://doi.org/10.1007/s10836-011-5238-3

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  • DOI: https://doi.org/10.1007/s10836-011-5238-3

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