Skip to main content
SpringerLink
Log in

Analog Circuit Fault Detection Using Location of Poles

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A method for detection of parametric faults occurring in linear analog circuits based on location of poles of the Circuit Under Test (CUT) is proposed. In the proposed method, the value of each component of the CUT is varied within its tolerance limit using monte carlo simulation. The upper and lower bounds of magnitude, phase angle, real part and imaginary part of all poles of the CUT are obtained. While testing, the locations of poles are obtained. If any one or more of the poles lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is validated through two benchmark circuits like second order sallenkey band pass filter and fourth order leapfrog low pass filter.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4

References

  1. Alippi C, Catelani M, Fort A, Mugnaini M (2002) SBT soft fault diagnosis in analog electronic circuits: a sensitivity-based approach by randomized algorithms. IEEE Trans Instrum Meas 51:116–1125

    Article  Google Scholar 

  2. Aminian M, Aminian F (2007) A modular fault diagnostic system for analog electronic circuits using neural networks with wavelet transform as a preprocessor. IEEE Trans Instrum Meas 56:1546–1554

    Article  Google Scholar 

  3. Guo Z, Savir J (2006) Coefficient based test of parametric faults in analog circuits. IEEE Trans Instrum Meas 55:150–157

    Article  Google Scholar 

  4. Jantos P, Grzechca D (April 16–18, 2008) “The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features”, Proceedings of the IEEE-DDECS’08, Slovakia, Europe

  5. Kavithamani A, Manikandan V, Devarajan N (November 23–26, 2009) “Analog Circuit Fault Diagnosis Based on Bandwidth and Fuzzy Classifier”, Proceedings of international conference, IEEE – TENCON 2009, pp 1–6, Singapore

  6. Manikandan V, Devarajan N (October 2007) “SBT Approach towards analog circuit fault diagnosis”, Active and Passive Electronic Components, Hindawi Publishing Corporation, USA, pp 1-11

  7. Papakostas DK, Hatzopoulos AA (2008) Unified procedure for fault detection of analog and mixed-mode circuits using magnitude and phase components of the power supply current spectrum. IEEE Trans Instrum Meas 57:2589–2595

    Article  Google Scholar 

  8. Saberi A, Stoorvogel AA, Sannuti P (2007) “Filtering Theory: with Applications to Fault Detection, Isolation and Estimation”, Springer

  9. Sindia S, Singh V, Agarwal VD (May 10–12, 2009) “Polynomial Coefficient Based DC Testing of Non Linear Analog Circuits”, GLSVLSI’09, Massachusetts, USA, pp 69–74

  10. Tadeusiewicz M, Hałgas S (2006) An algorithm for multiple fault diagnosis in analogue circuits. Int J Circ Theor Appl 34:607–615

    Article  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Coimbatore Institute of Technology, Coimbatore, 641 014, India

    Ashok Kavithamani & Venugopal Manikandan

  2. Department of Electrical and Electronics Engineering, Government College of Technology, Coimbatore, 641 013, India

    Nanjundappan Devarajan

Authors
  1. Ashok Kavithamani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Venugopal Manikandan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nanjundappan Devarajan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ashok Kavithamani.

Additional information

Responsible Editor: K.K. Saluja

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kavithamani, A., Manikandan, V. & Devarajan, N. Analog Circuit Fault Detection Using Location of Poles. J Electron Test 27, 673–678 (2011). https://doi.org/10.1007/s10836-011-5240-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5240-9

Keywords

Search

Navigation