Abstract
This paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures.
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Acknowledgment
Authors thanks Dr. Gary Swift from Xilinx Corporation for his support to the X-TMR version of the application, Dr. Vincent Pouget, from IMS/CNRS, for his support for laser test experiments and finally M. Guy Berger, from UCL, for his support will performing heavy ion ground testing.
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Foucard, G., Peronnard, P. & Velazco, R. Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions. J Electron Test 27, 627–633 (2011). https://doi.org/10.1007/s10836-011-5245-4
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DOI: https://doi.org/10.1007/s10836-011-5245-4