Abstract
Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.
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References
Agarwal A, Blaauw D, Zolotov V, Sundareswaran S, Zhao M, Gala K, Panda R (2003) Statistical delay computation considering spatial correlations. In: IEEE ASP-DAC, pp 271–276
Aitken RC (2006) Defect-oriented testing. In: Gizopoulos D (ed) Advances in electronic testing: challenges and methodologies. Springer, New York
Baker K, Gronthoud G, Lousberg M, Schanstra I, Hawkins C (1999) Defect-based delay testing of resistive vias-contacts a critical evaluation. In: IEEE international test conference, pp 467–476
Cochran WG (1977) Sampling techniques, 3rd edn. Wiley, New York
Cole E Jr, Tangyunyong P, Hawkins C, Bruce MR, Bruce VJ, Ring RM, Chong W-L (2001) Resistive interconnection localization. In: 27th international symposium for testing and failure analysis, pp 15–21
Czutro A, Houarche N, Engelke P, Polian I, Comte M, Renovell M, Becker B (2008) A simulator of small-delay faults caused by resistive-open defects. In: IEEE European test symposium, pp 113–118
García-Gervacio JL, Champac V (2010) Computing the detection of small delay defects caused by resistive opens of nanometer ICs. In: IEEE European test symposium
Goel SK, Devta-Prasanna N, Turakhia RP (2009) Effective and efficient test pattern generation for small delay defect. In: IEEE VLSI test symposium, pp 111–116
Goncalves FM, Texeira JP (1999) Defect-oriented sampling of non-equally probable faults in VLSI systems. J Electron Test: Theory Appl 15:41–52
Kapur R, Zegda J, Williams, T (2007) Fundamentals of timing information for test: how simple can we get? In: IEEE international test conference, pp 1–7
Kang K, Paul BC, Roy K (2005) Statistical timing analysis using levelized covariance propagation. In: IEEE proc. of the design, automation and test in Europe conference
Kruseman B, Majhi AK, Gronthoud G, Eichenberger S (2004) On hazard-free patterns for fine-delay fault testing. In: IEEE international test conference, pp 213–222
Li Z, Lu X, Qiu W, Shi W, Walker DMH (2003) A circuit level fault model for resistive opens and bridges. In: Proceedings of the 21st IEEE VLSI test symposium, pp 379–384
Li Z, Lu X, Qiu W, Shi W, Walker DMH (2003) A circuit level fault model for resistive bridges. In: ACM transactions on design automation of electronic systems (TODAES), vol 8, no 4, pp 546–559
Lin X, Kassab M, Rajski J (2007) Test generation for timing-critical transition faults. In: Proc. Asian test symposium, pp 493–500
Lin X, Tsai K-H, Wang C, Kassab M, Rajski J, Kobayashi T, Klingenberg R, Sato Y, Hamada S, Aikyo T (2006) Timing-aware ATPG for high quality at-speed testing of small delay defects. In: Proc. Asian test symposium, pp 111–116
Liou J-J, Chen K-T, Mukherjee DA, Kundu S (2000) Performance sensitivity analysis using statistical methods and its applications. In: Design automation conference, pp 587–592
Liou J-J, Krstic A, Jiang Y-M, Chen K-T (2003) Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. In: IEEE transactions on computer-aided design of integrated circuits and systems, pp 756–769
Liou J-J, Wang L-C, Cheng K-T, Dworak J, Mercer MR, Kapur R, Williams TW (2002) Analysis of delay test effectiveness with a multiple-clock scheme. In: IEEE international test conference, pp 407–416
Mattiuzzo R, Appello D, Allsup C (2009) Small-delay-defect testing: SDD automatic test-pattern generation breaks the nanometer quality barrier. [Online]. Available: http://www.tmworld.com/article/CA6660051.html
Montgomery DC, Runger GC (2003) Applied statistics and probability for engineers, 3rd edn. Wiley, New York
Needham W, Prunty C, Yeoh EH (1998) High voltage microprocessor test escapes an analysis of defects our tests are missing. In: IEEE international test conference, pp 25–34
Nigh P, Gattiker A (2000) Test method evaluation experiments & data. In: IEEE international test conference, pp 454–463
Park ES, Mercer MR, Williams TW (1992) The total delay fault model and statistical delay fault coverage. IEEE Trans Comput 41(6):688–698
Rice JA (1995) Mathematical statistics and data analysis, 2nd edn. ITP, Duxbury Press
Rodríguez-Montañés R, Pineda de Gyvez J, Volf P (2002) Resistance characterization for weak open defects. IEEE Des Test Comput 19(5):18–26
Rosselló JL, de Benito C, Bota SA, Segura J (2007) Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. In: IEEE design, automation and test in Europe, pp 1271–1276
Sakurai T, Newton R (1991) Delay analysis of series-connected MOSFET circuits. IEEE JSSC 26(2):122–131
Sato Y, Hamada S, Maeda T, Takatori A, Kajihara S (2005) Evaluation of the statistical delay quality model. In: Asia South Pacific design automation conference, pp 305–310
Sengupta S, Kundu S, Chakravarty S, Parvathala P (1999) Defect-based test: a key enabler for successful migration to structural test. Intel Technol J 1:1–14
Stamper A, McDevitt T, Luce S (1998) Sub-0.25-micron interconnect scaling: damascene copper versus substractive aluminum. In: IEEE adv. semiconductors manufacturing conference, pp 337–346
Tayade R, Sundereswaran S, Abraham J (2007) Small-delay defect detection in the presence of process variations. In: IEEE international symposium on quality electronic design, pp 711–716
Uzzaman A, Tegethoff M, Li B, Mc Cauley K, Hamada S, Sato Y (2006) Not all delay tests are the same - SDQL model shows true-time. In: Proc. Asian test symposium, pp 147–152
Weisstein EW (0000) Erfc. From MathWorld–a Wolfram web resource. [Online]. Available: http://mathworld.wolfram.com/Erfc.html
Yilmaz M, Chakrabarty K, Tehranipoor M (2008) Test-pattern grading and pattern selection for small-delay defects. In: IEEE VLSI test symposium, pp 233–239
Zolotov V, Xiong J, Fatemi H, Visweswariah C (2008) Statistical path selection for At-speed test. In: IEEE/ACM international conference on computer-aided design, pp 624–631
Acknowledgment
The work has been partially supported by CONACYT (Mexico) through the PhD scholarship No. 166649. The authors would like to thank Baris Arslan (from UCSD) for his valuable comments on this paper.
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García-Gervacio, J.L., Champac, V. Computing the Detection Probability for Small Delay Defects of Nanometer ICs. J Electron Test 27, 741–752 (2011). https://doi.org/10.1007/s10836-011-5256-1
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DOI: https://doi.org/10.1007/s10836-011-5256-1