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A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement

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Abstract

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

    Hyun Jin Kim & Jacob A. Abraham

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  1. Hyun Jin Kim
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  2. Jacob A. Abraham
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Correspondence to Hyun Jin Kim.

Additional information

Responsible Editor: D. Keezer

This manuscript is an extended version of a paper presented at the 15th IEEE European Test Symposium, May 2010.

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Kim, H.J., Abraham, J.A. A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement. J Electron Test 28, 585–597 (2012). https://doi.org/10.1007/s10836-012-5324-1

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  • DOI: https://doi.org/10.1007/s10836-012-5324-1

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