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Structural Test and Diagnosis for Graceful Degradation of NoC Switches

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Abstract

Networks-on-Chip (NoCs) are implicitly fault tolerant and due to their inherent redundancy they can overcome defective cores, links and switches. This effect can be used to increase yield at the cost of reduced performance. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions of a defective network switch rather than providing only a pass/fail result for the complete switch. To achieve this, the new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects. This allows to disable defective parts of a switch after production test and use the intact functions. Thereby, only a minimum performance decrease is induced while the yield is increased. According to the experimental results, the method improves the performability of NoCs since 56.86 % and 72.42 % of defects in two typical switch models only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with many common switch designs.

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Acknowledgement

Part of this work was funded by the DFG project ROCK under Wu 245/12-1.

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Authors and Affiliations

  1. Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569, Stuttgart, Germany

    Atefe Dalirsani, Stefan Holst, Melanie Elm & Hans-Joachim Wunderlich

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  1. Atefe Dalirsani
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  2. Stefan Holst
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  3. Melanie Elm
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  4. Hans-Joachim Wunderlich
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Correspondence to Atefe Dalirsani.

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Responsible Editor: C. Metra

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Dalirsani, A., Holst, S., Elm, M. et al. Structural Test and Diagnosis for Graceful Degradation of NoC Switches. J Electron Test 28, 831–841 (2012). https://doi.org/10.1007/s10836-012-5329-9

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  • DOI: https://doi.org/10.1007/s10836-012-5329-9

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