Abstract
Due to the continuous technology scaling, soft error becomes a major reliability issue at nanoscale technologies. Single or multiple event transients at low levels can result in multiple correlated bit flips at logic or higher abstraction levels. Addressing this correlation is essential for accurate low-level soft error rate estimation, and more importantly, for the cross-level error abstraction, e.g. from bit errors at logic level to word errors at register-transfer level. This paper proposes a novel error estimation method to take into consideration both signal and error correlations. It unifies the treatment of error-free signals and erroneous signals, so that the computation of error probabilities and correlations can be carried out using techniques for signal probabilities and correlations calculation. The proposed method not only reports accurate error probabilities when internal gates are impaired by soft errors, but also gives quantification of the error correlations in their propagation process. This feature enables our method to be a versatile technique used in high-level error estimation. The experimental results validate our proposed technique showing that compared with Monte-Carlo simulation, it is 5 orders of magnitude faster, while the average inaccuracy of error probability estimation is only 0.02.
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Notes
As Monte-Carlo simulation can not obtain the exact results either, the inaccuracy here actually means the deviation of our estimated error probabilities from the results reported by Monte-Caro simulation.
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This work was partly supported by the German Research Foundation (DFG) as part of the national focal program ”Dependable Embedded Systems”. (SPP-1500, http://spp1500.ira.uka.de/)
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Chen, L., Ebrahimi, M. & Tahoori, M.B. CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis. J Electron Test 29, 143–158 (2013). https://doi.org/10.1007/s10836-013-5365-0
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DOI: https://doi.org/10.1007/s10836-013-5365-0