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CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis

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Abstract

Due to the continuous technology scaling, soft error becomes a major reliability issue at nanoscale technologies. Single or multiple event transients at low levels can result in multiple correlated bit flips at logic or higher abstraction levels. Addressing this correlation is essential for accurate low-level soft error rate estimation, and more importantly, for the cross-level error abstraction, e.g. from bit errors at logic level to word errors at register-transfer level. This paper proposes a novel error estimation method to take into consideration both signal and error correlations. It unifies the treatment of error-free signals and erroneous signals, so that the computation of error probabilities and correlations can be carried out using techniques for signal probabilities and correlations calculation. The proposed method not only reports accurate error probabilities when internal gates are impaired by soft errors, but also gives quantification of the error correlations in their propagation process. This feature enables our method to be a versatile technique used in high-level error estimation. The experimental results validate our proposed technique showing that compared with Monte-Carlo simulation, it is 5 orders of magnitude faster, while the average inaccuracy of error probability estimation is only 0.02.

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Notes

  1. As Monte-Carlo simulation can not obtain the exact results either, the inaccuracy here actually means the deviation of our estimated error probabilities from the results reported by Monte-Caro simulation.

References

  1. Asadi H, Tahoori M (2006) Soft error derating computation in sequential circuits. In: IEEE/ACM international conference on computer-aided design, pp 497–501

  2. Baraza J, Gracia J, Blanc S, Gil D, Gil P (2008) Enhancement of fault injection techniques based on the modification of VHDL code. IEEE Trans Very Large Scale Integr Syst 16(6):693–706

    Article  Google Scholar 

  3. Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266

    Article  Google Scholar 

  4. Bhanja S, Ranganathan N (2004) Cascaded bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans Very Large Scale Integr Syst 12(12):1360–1370

    Article  Google Scholar 

  5. Borkar S (2005) Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6):10–16

    Article  Google Scholar 

  6. Chen L, Tahoori M (2012a) An efficient probability framework for error propagation and correlation estimation. In: IEEE international on-line testing symposium Barcelona, Spain, pp 170–175

  7. Chen L, Tahoori M (2012b) Soft error propagation and correlation estimation in combinational network. In: The first workshop on manufacturable and dependable multicore architectures at nanoscale (MEDIAN’12), Annecy, France

  8. Choudhury M, Mohanram K (2009) Reliability analysis of logic circuits. IEEE Trans Comput-Aided Des Integr Circ Syst 28(3):392–405

    Article  Google Scholar 

  9. Costa JC, Silveira LM, Devadas S, Monteiro J (2004) Power estimation using probability polynomials. Design Automation for Embedded Systems, pp 19–52

  10. Csárdi G, Nepusz T (2006) The igraph software package for complex network research. InterJournal Vol Complex Systems 1695

  11. Entrena L, Garcia-Valderas M, Fernandez-Cardenal R, Lindoso A, Portela M, Lopez-Ongil C (2012) Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. IEEE Trans Comput 61(3):313–322

    Article  MathSciNet  Google Scholar 

  12. Ercolani S, Favalli M, Damiani M, Olivo P, Ricco B (1989) Estimate of signal probability in combinational logic networks. In: European test conference, pp 132–138

  13. Fazeli M, Ahmadian S, Miremadi S, Asadi H, Tahoori M (2011) Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). In: Proceedings of design, automation and test in Europe, pp 1–6

  14. Gill B, Seifert N, Zia V (2009) Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In: IEEE international reliability physics symposium, pp 199–205

  15. Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) Mibench: a free, commercially representative embedded benchmark suite. In: IEEE international workshop on workload characterization, pp 3–14

  16. Han J, Chen H, Boykin E, Fortes J (2011) Reliability evaluation of logic circuits using probabilistic gate models. Microelectron Reliab 2:468–476

    Google Scholar 

  17. Kretzschmar U, Astarloa A, Lazaro J, Jimenez J, Zuloaga A (2011) An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAs. In: International symposium on system on chip (SoC), pp 96–101

  18. Krishnaswamy S, Viamontes G, Markov I, Hayes J (2005) Accurate reliability evaluation and enhancement via probabilistic transfer matrices. In: Proceedings of design, automation and test in Europe, pp 282–287

  19. Li X, Adve SV, Bose P, Rivers JA (2005) SoftArch: an architecture-level tool for modeling and analyzing soft errors. In: International conference dependable systems and networks, pp 496–505

  20. Mahatme N, Jagannathan S, Loveless T, Massengill L, Bhuva B, Wen SJ, Wong R (2011) Comparison of combinational and sequential error rates for a deep submicron process. IEEE Trans Nucl Sci 58(6):2719–2725

    Article  Google Scholar 

  21. Marculescu R, Marculescu D, Pedram M (1998) Probabilistic modeling of dependencies during switching activity analysis. IEEE Trans Comput-Aided Des Integr Circ Syst 17(2):73–83

    Article  Google Scholar 

  22. Miskov-Zivanov N, Marculescu D (2006) Circuit reliability analysis using symbolic techniques. IEEE Trans Comput-Aided Des Integr Circ Syst 25(12):2638–2649

    Article  Google Scholar 

  23. Miskov-Zivanov N, Marculescu D (2010) Multiple transient faults in combinational and sequential circuits: a systematic approach. IEEE Trans Comput-Aided Des Integr Circ Syst 29(10):1614–1627

    Article  Google Scholar 

  24. Mohyuddin N, Pakbaznia E, Pedram M (2008) Probabilistic error propagation in logic circuits using the Boolean difference calculus. In: IEEE International conference on computer design, pp 7–13

  25. Mukherjee S, Emer J, Reinhardt S (2005) The soft error problem: an architectural perspective. In: International symposium on high-performance computer architecture, pp 243–247

  26. OpenRISC Project (2012) http://opencores.org/openrisc

  27. Papoulis A (1990) Probability & statistics. Prentice Hall, Englewood Cliffs

    MATH  Google Scholar 

  28. Rajaraman R, Kim JS, Vijaykrishnan N, Xie Y, Irwin MJ (2006) SEAT-LA: a soft error analysis tool for combinational logic. In: International conference on VLSI design, pp 499–502

  29. Rao R, Chopra K, Blaauw D, Sylvester D (2006) An efficient static algorithm for computing the soft error rates of combinational circuits. In: Proceedings of design, automation and test in Europe, pp 1–6

  30. Rejimon T, Lingasubramanian K, Bhanja S (2009) Probabilistic error modeling for nano-domain logic circuits. IEEE Trans Very Large Scale Integr Syst 17(1):55–65

    Article  Google Scholar 

  31. Rossi D, Omana M, Toma F, Metra C (2005) Multiple transient faults in logic: an issue for next generation ics?. In: IEEE international symposium on defect and fault tolerance in VLSI systems, pp 352–360

  32. Rubinstein R, Kroese D (2008) Simulation and the Monte Carlo method. Wiley, New York

    MATH  Google Scholar 

  33. Sanda P, Kellington J, Kudva P, Kalla R, McBeth R, Ackaret J, Lockwood R, Schumann J, Jones C (2008) Soft-error resilience of the IBM POWER6 processor. IBM J Res Dev 52(3):275–284

    Article  Google Scholar 

  34. Shivakumar P, Kistler M, Keckler S, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. In: International conference on dependable systems and networks, pp 389–398

  35. Sivaswamy S, Bazargan K, Riedel M (2009) Estimation and optimization of reliability of noisy digital circuits. In: International symposium on quality of electronic design, pp 213–219

  36. Wang N, Quek J, Rafacz T, Patel S (2004) Characterizing the effects of transient faults on a high-performance processor pipeline. In: International conference on dependable systems and networks, pp 61–70

  37. Yu C, Hayes J (2011) Trigonometric method to handle realistic error probabilities in logic circuits. In: Proceedings of design, automation and test in Europe, pp 1–6

  38. Zhang B, Wang W, Orshansky M (2006) FASER: fast analysis of soft error susceptibility for cell-based designs. In: International symposium on quality electronic design

  39. Zhang M, Shanbhag N (2006) Soft-Error-Rate-Analysis (SERA) methodology. IEEE Trans Comput-Aided Des Integr Circ Syst 25(10):2140–2155

    Article  Google Scholar 

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Acknowledgments

This work was partly supported by the German Research Foundation (DFG) as part of the national focal program ”Dependable Embedded Systems”. (SPP-1500, http://spp1500.ira.uka.de/)

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Correspondence to Liang Chen.

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Responsible Editor: H. Manhaeve

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Chen, L., Ebrahimi, M. & Tahoori, M.B. CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis. J Electron Test 29, 143–158 (2013). https://doi.org/10.1007/s10836-013-5365-0

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  • DOI: https://doi.org/10.1007/s10836-013-5365-0

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