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High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design

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Abstract

In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit’s inputs. Experimental results, simulated in 45 nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.

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References

  1. Avirneni NDP, Somani AK (2012) Low overhead soft error mitigation techniques for high-performance and aggressive designs. IEEE Trans Comput 61:488–501. doi:10.1109/TC.2011.31

    Article  MathSciNet  Google Scholar 

  2. Baumann RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and Materials Reliability. IEEE Trans Device Mater Reliab 5:305–316. doi:10.1109/TDMR.2005.853449

    Article  Google Scholar 

  3. Berkeley predictive technology model (2007) http://www.eas.asu.edu/~ptm/

  4. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43:2874–2878. doi:10.1109/23.556880

    Article  Google Scholar 

  5. Carreno VA, Choi G, and Iyer RK (1990) Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system. In NASA Tech Memorandum 4241

  6. Cha H, Patel JH (1993) A logic-level model for α-particle hits in CMOS circuits. Proc IEEE Int Conf Comput Des :538–542. doi:10.1.1.34.8586

  7. Chen M, Orailoglu A (2009) Flip-flop hardening and selection for soft error and delay fault resilience. In Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst :49–57. doi:10.1109/DFT.2009.50

  8. Choi Y, Kim Y, Lombardi F (2012) Soft error masking latch for sub-threshold voltage operation. In Proc IEEE Int Midwest Symp Circuits Syst :25–28. doi:10.1109/MWSCAS.2012.6291948

  9. Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Device Mat Rel 50:583–602. doi:10.1109/TNS.2003.813129

    Google Scholar 

  10. Hazucha P, Karnik T, Walstra S, Bloechel BA, Tschanz JW, Maiz J, Soumyanath K, Dermer GE, Narendra S, De V, Borkar S (2004) Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE J Solid State Circuits 39:1536–1543. doi:10.1109/CICC.2003.1249472

    Article  Google Scholar 

  11. Karnik T, Hazucha P, Patel J (2004) Characterization of soft error caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput 1:128–143. doi:10.1109/TDSC.2004.14

    Article  Google Scholar 

  12. Kim L-S, Dutton RW (1990) Metastability of CMOS latch/flip-flop. IEEE J Solid State Circuits 25:942–951. doi:10.1109/4.58286

    Article  Google Scholar 

  13. Lin S, Kim YB, Lombardi F (2011) Design and performance evaluation of radiation hardened latches for nanoscale CMOS. IEEE Trans Large Scale Integr (VLSI) Syst 19:1315–1319. doi:10.1109/TVLSI.2010.2047954

    Article  Google Scholar 

  14. Mitra S, Zhang M, Waqas S, Seifert N, Gill B, Kim KS (2006) Combinational logic soft error correction. In Proc IEEE Int’l Test Conf :824–832. doi:10.1109/TEST.2006.297681

  15. Omana M, Rossi D, Metra C (2003) Novel transient fault hardened static latch. In Proc IEEE Int Test Conf :886–892. doi:10.1109/TEST.2003.1271074

  16. Omana M, Rossi D, Metra C (2007) Latch susceptibility to transient faults and new hardening approach. IEEE Trans Comput 56:1255–1268. doi:10.1109/TC.2007.1070

    Article  MathSciNet  Google Scholar 

  17. Rey DM (2009) The MOSIS Service. http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html

  18. Sasaki Y, Namba K, Ito H (2006) Soft error masking circuit and latch using Schmitt trigger circuit. In Proc IEEE DFT :327–335. doi:10.1109/DFT.2006.60

  19. Seifert N, Zhu X, Massengill LW (2002) Impact of scaling on soft error rates in commercial microprocessors. IEEE Trans Nucl Sci 49:3100–3106. doi:10.1109/TNS.2002.805402

    Article  Google Scholar 

  20. Zyuban V (2003) Optimization of scannable latches for low energy. IEEE Trans Very Large Scale Integr (VLSI) Syst 11:778–788. doi:10.1109/TVLSI.2003.814322

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Guilan, Rasht, 41996-13769, Iran

    Rahebeh Niaraki Asli & Saeideh Shirinzadeh

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  1. Rahebeh Niaraki Asli
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  2. Saeideh Shirinzadeh
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Correspondence to Rahebeh Niaraki Asli.

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Responsible Editor: C. A. Papachristou

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Niaraki Asli, R., Shirinzadeh, S. High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design. J Electron Test 29, 537–544 (2013). https://doi.org/10.1007/s10836-013-5384-x

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  • DOI: https://doi.org/10.1007/s10836-013-5384-x

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