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On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment

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Abstract

This paper deals with the performance of a Carbon Nano Tube Field Effect Transistor (CNTFET) in the presence of undeposited CNTs as defects. A simulation-based analysis of delay degradation due to different features (such as chirality and defective CNT distribution) is initially pursued. Two solutions to mitigate the change in delay are proposed; these approaches are based on adjusting the gate width of the CNTFET by lithography (and removing CNTs) as part of the fabrication process. These two methods reduce the average delay and its deviation, respectively. A probabilistic delay analysis is then presented. The performance of the proposed two adjustment methods is evaluated by considering CNT features (such as chirality and defect distribution) deterministically and probabilistically. By deterministic (probabilistic) simulation, the first method reduces on average the delay by 6.968 % (7.811 %) while the deviation is increased (decreased) by 32.444 % (9.788 %). The second method reduces deterministically (probabilistically) on average the deviation by 44.159 % (47.476 %) with 2.166 % (4.409 %) delay reduction.

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References

  1. Alberto Leon-Garcia (1994) “Probability and random processes for electrical engineering, 2nd edition,” Addison Wesley

  2. Ashraf R, Nain RK, Chrzanowska-Jeske M, Narendra SV (2010) “Design methodology for carbon nanotube based circuits in the presence of metallic tubes,” Proc. IEEE/ACM Symposium on Nano Architectures, pp. 71–76, Anaheim

  3. Cho G, Lombradi F, Kim Y-B (2011) Modeling undeposited CNTs for CNTFET operation. IEEE Transactions on Device and Materials Reliability 1(2):263–272

    Article  Google Scholar 

  4. CNFET Models. http://nano.stanford.edu/models.php

  5. Collins PG, Arnold MS, Avouris P (2001) Engineerig carbon nanotubes and nanotube circuits using electrical breakdown. Science 292:706–709

    Article  Google Scholar 

  6. Deng J, Wong H-SP (2007) A compact SPICE model for Carbon-Nanotube Field-Effect Transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Transactions on Electron Devices 54:3186–3194

    Article  Google Scholar 

  7. Deng J, Wong H-SP (2007) A compact SPICE model for Carbon Nanotube Field Effect Transistors including non-idealities and its application—Part II: full device model and circuit performance benchmarking. IEEE Transactions on Electron Devices 54:3195–3205

    Article  Google Scholar 

  8. FETTOY Model. http://nanohub.org/

  9. Hassanien A et al (2005) Selective etching of metallic single-wall carbon nonotubes with hydrogenl plasma. Nanotechnlology 16:278–281

    Article  Google Scholar 

  10. Patil N, Deng J, Lin A, Wong H-SP, Mitra S (2008) Design methods for misaligned and mispositioned carbon-nanotube immune circuits. IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems 27:1725–1736

    Article  Google Scholar 

  11. Patil N, Deng J, Mitra S, Wong H-SP (2009) Circuit-level performance benchmarking and scalability of carbon nanotube transistor circuits. IEEE Transaction on Nanotechnology 8(1):37–45

    Article  Google Scholar 

  12. Patil N, Lin A, Myers E, Ryu K, Badmaev A, Zhou C, Wong H-SP, Mitra S (2009) Wafer-scale growth and transfer of aligned single-walled carbon nanotubes. IEEE Trans Nanotechnol 8:498–504

    Article  Google Scholar 

  13. Qu L, Feng D, Dai L (2008) Preferential syntheses of semiconducting vertically aligned single-walled carbon nanotubes for direct use in FETs. Nano Letters 8(9):2682–2687

    Article  Google Scholar 

  14. Rabaey JM, Chandrakasan A, Nikolic B (2002) “Digital integrated circuits: a design perspective, 2nd edition,” Prentice Hall

  15. Southampton CNT Model. http://www.cnt.ecs.soton.ac.uk

  16. Zhang J, Patil N, Mitra S (2009) Probabilistic analysis and design of Metallic-Carbon-Nanotube-Tolerant digital logic circuits. IEEE Transaction on Computer-Aided Design 28:1307–1320

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, 02115, USA

    Geunho Cho & Fabrizio Lombardi

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  1. Geunho Cho
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  2. Fabrizio Lombardi
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Correspondence to Fabrizio Lombardi.

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Responsible Editor: M. Violante

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Cho, G., Lombardi, F. On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment. J Electron Test 29, 261–273 (2013). https://doi.org/10.1007/s10836-013-5388-6

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  • DOI: https://doi.org/10.1007/s10836-013-5388-6

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