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Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop

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Abstract

This paper presents a construction of timing-error-detecting dual-edge-triggered flip-flops (DET-FFs). The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with relatively large area, the proposed FF uses internal signals in a DET-FF as as an alternative to the transition detector. This paper also shows an evaluation result indicating that the proposed FF has smaller area overhead than the simple combination of the conventional DET-FF and timing error detection methods.

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Acknowledgments

This work was supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc. and Mentor Graphics, Inc.

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Authors and Affiliations

  1. Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba, 263-8522, Japan

    Kazuteru Namba, Takashi Katagiri & Hideo Ito

Authors
  1. Kazuteru Namba
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  2. Takashi Katagiri
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  3. Hideo Ito
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Corresponding author

Correspondence to Kazuteru Namba.

Additional information

The earlier version of this paper was presented at the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’12).

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Namba, K., Katagiri, T. & Ito, H. Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. J Electron Test 29, 545–554 (2013). https://doi.org/10.1007/s10836-013-5392-x

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  • DOI: https://doi.org/10.1007/s10836-013-5392-x

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