Abstract
This paper presents a low-cost test technique for testing high-voltage laterally diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to identify structural defects such as gate-FOX breakdown, post breakdown thermal stress and drain leakage due to high voltages. A novel highly accurate hybrid MOS-p model for HV-LDMOS was developed and validated across various device geometries including both long and small gate-channels. Structural defects in HV-LDMOS were modeled and their physical effect was induced in the hybrid MOS-p model to develop fault models. These fault models were used for parametric testing and diagnosis of HV-LDMOS. A novel test technique using a noise-reduction scheme to test HV-LDMOS is presented in this paper. Test simulations were performed on a MOSFET driver IC with a 700 V LDMOS and experimental validation was performed by building a prototype test setup and making hardware measurements for breakdown and leakage tests. This test technique overcomes the test challenges pertaining to power supply and tester system noise, and provides a superior signal-to-noise ratio (SNR) when compared to conventional test methods. The noise-reduction scheme is inexpensive and highly accurate. The fault-model based test approach reduces the test suite for HV-LDMOS to a couple of test measurements which reduces the overall test cost and time.
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References
Ballan H, Declercq M (1998) HV devices & circuits in standard CMOS technologies, Kluwer, pp.156–167
Belaid MA, Ketata K, Masmoudi M, Gares M, Maanane H, Marcon J (2006) Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests. Microelectron Reliab 46:1800–1805
Buck KM, Li HW, Subramanian S, Hess HL, Mojarradi M (2003) Development and testing of high-voltage devices fabricated in standard CMOS and SOI technologies. NASA 11th Symposium
Dolny GM, Nostrand GE, Hill KE (1992) The effect of temperature on lateral DMOS transistors in a power IC technology. IEEE Transactions on Electronic Devices 39(4):990–995
Efland TR (2001) Integration of power devices in advanced mixed signal analog BiCMOS technology. Microelectron J 32:409–418
Efland T, Tsai CY, Erdeljac J, Mitros J, Hutter L (1997) A performance comparison between new reduced surface drain ‘RSD’ LDMOS and RESURF and conventional planar power devices rated at 20 V. Proceedings of the IEEE International Symposium on Power Semiconductor Devices and IC’s, pp. 185–188
Frere SF, Moens P, Desoete B, Wojciechowski D, Walton AJ (2005) An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions. Proceedings of the International Conference on Microelectronic Test Structures 75–79
Hower P, Lin J, Pendharkar S, Hu B, Arch J, Smith J, Efland T (2005) A rugged LDMOS for LBC5 technology. International Symposium on Power Semiconductor Devices and IC’s
Hower P, Lin J, Pendharkar S, Hu B, Arch J, Smith J, Efland T (2005) A rugged LDMOS for LBC5 technology. Proceedings of the 17th International Symposium on Power Semiconductor Devices and IC’s, pp. 327–330
Jiayi X, Yanling S, Zheng R, Shaojian H, Shoumian C, Yuhang Z, Yanfang D, Zongsheng L (2008) An optimized scalable BSIM Macromodel for HV double-diffused drain MOSFET I-V characteristics. IEEE Transactions on Power Electronics 23(2):1027–1030
Jing Z, Qinsong Q, Weifeng S, Siyang L (2010) Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress. J Semicond 31(1)
Kannan S, Kim B, Taenzler F, Antley R (2012) Development of scalable electrical model for high-voltage LDMOS. Proceedings of 7th International Power Electronics and Motion Control Conference, pp. 5–9
Kannan S, Kim B, Taenzler F, Antley R, Moushegian K, Gupta A (2013) Physics based fault models for testing high-voltage LDMOS. Proceedings of 26th VLSI Design Conference
Malandruccolo V, Ciappa M, Rothleitner H, Fichtner W (2011) A new built-in defect-based testing technique to achieve zero defects in the automotive environment. Journal of Electronic Testing Theory and Applications – Special Issue in Analog, Mixed-signal, RF and MEMS Testing 27(1):19–30
Moens P, Reynders K (2005) On the electrical SOA of integrated vertical DMOS transistors. IEEE Electron Device Letters 26(4):270–272
Myono T, Nishibe E, Iwatsu K, Kikuchi S, Suzuki T, Sasaki Y, Itoh K, Kobayashi H (1998) Modelling technique for high-voltage MOS device with BSIM3v3. IEEE Electronics Letters 34(18):1790–1791
Park HS (2010) Effects of trench oxide and field plates on the breakdown voltage of SOI LDMOSFET. Curr Appl Phys 10:419–421
Posch W, Murhammer C, Seebacher E (2009) Test structure for high-voltage LD-MOSFET mismatch characterization in 0.35 μm HV-CMOS technology. International Conference on Microelectronic Test Structures
Ren Z, Hu SJ, Shi YL, Zhu J, Chen SM, Zhao YH (2006) Optimization of BSIM3 I-V model for double diffused drain HV MOS. Proceedings of the 8th International Conference on Solid-State and Integrated-Circuit Technology, pp. 1349–1351
Subramaniam Y, Lauritzen PO, Green KR (1999) A compact model for an IC lateral diffused MOSFET using the lumped-charge methodology. Modeling and Simulation of Microsystems
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Kannan, S., Kannan, K., Kim, B.C. et al. Physics-Based Low-Cost Test Technique for High Voltage LDMOS. J Electron Test 29, 745–762 (2013). https://doi.org/10.1007/s10836-013-5417-5
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DOI: https://doi.org/10.1007/s10836-013-5417-5