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Effective Timing Error Tolerance in Flip-Flop Based Core Designs

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Abstract

Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.

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References

  1. Agarwal M, Paul BC, Zhang M, Mitra S (2007) Circuit failure prediction and its application to transistor aging. IEEE VLSI Test Symp 277–284

  2. Agarwal M, Balakrishnan V, Bhuyan A, Kim K, Paul BC, Wang W, Yang B, Cao Y, Mitra S (2008) Optimized circuit failure prediction for aging: practicality and promise. IEEE Int Test Conf 26.1

  3. Anghel L, Nicolaidis M (2000) Cost reduction and evaluation of temporary faults detecting technique. Des Autom Test Eur Conf 591–598

  4. Austin T, Blaauw D, Mudge T, Flautner K (2004) Making typical silicon matter with razor. IEEE Comput 37(3):57–65

    Article  Google Scholar 

  5. Bowman K, Tschanz JW, Kim N-S, Lee JC, Wilkerson CB, Lu S-L, Karnik T, De VK (2009) Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE J Solid State Circuits 44(1):49–63

    Article  Google Scholar 

  6. Bowman K, Tschanz JW, Lu S-L, Aseron PA, Khellah MM, Raychowdhury A, Geuskens BM, Tokunaga C, Wilkerson CB, Karnik T, De VK (2011) A 45nm resilient microprocessor core for dynamic variation tolerance. IEEE J Solid State Circuits 46(1):194–208

    Article  Google Scholar 

  7. Bull D, Das S, Shivashankar K, Dasika GS, Flautner K, Blaauw DT (2011) A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. IEEE J Solid State Circuits 46(1):18–31

    Article  Google Scholar 

  8. Choudhury M, Chandra V, Mohanram K, Aitken R (2010) TIMBER: time borrowing and error relaying for online timing error resilience. ACM/IEEE Des Autom Test Eur Conf 1554–1559

  9. Das S, Tokunaga C, Pant S, Ma W-H, Kalaiselvan S, Lai K, Bull DM, Blaauw DT (2009) Razor II: in situ error detection and correction for PVT and SER tolerance. IEEE J Solid State Circuits 44(1):32–48

    Article  Google Scholar 

  10. Ernst D, Kim N-S, Das S, Pant S, Rao R, Pham T, Ziesler C, Blaauw D, Austin T, Flautner K, Mudge T (2003) Razor: a low-power pipeline based on circuit-level timing speculation. Int Symp Microarchitecture 7–18

  11. Floros A, Tsiatouhas Y, Arapoyanni A, Haniotakis Th (2006) A pipeline architecture incorporating a low-cost error detection and correction mechanism. IEEE Int Conf Electron Circ Syst 692–695

  12. Floros A, Tsiatouhas Y, Kavousianos X (2008) The time dilation scan architecture for timing error detection and correction. IFIP/IEEE Int Conf Very Large Scale Integr 569–574

  13. Imhof ME, Wunderlich H-J (2011) Soft error correction in embedded storage elements. IEEE Int On-Line Test Symp 169–174

  14. IWLS05 benchmark circuits: http://iwls.org/iwls2005/benchmarks.html

  15. Kang K, Park SP, Kim K, Roy K (2010) On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures. IEEE Tran VLSI Syst 18(2):270–280

    Article  Google Scholar 

  16. Matakias S, Tsiatouhas Y, Arapoyanni A, Haniotakis T (2004) A circuit for concurrent detection of soft and timing errors in digital CMOS ICs. J Electron Test Theory Appl 20(5):523–531

    Article  Google Scholar 

  17. Metra C, Degiampietro R, Favalli M, Ricco B (1999) Concurrent detection and diagnosis scheme for transient, delay and crosstalk faults. IEEE Int On-Line Test Workshop 66–70

  18. Mitra S, Seifert N, Zhang M, Shi Q, Kim KS (2005) Robust system design with built-in soft-error resilience. IEEE Comput 38(2):43–52

    Article  Google Scholar 

  19. Nicolaidis M (1999) Time redundancy based soft-error tolerance to rescue nanometer technologies. IEEE VLSI Test Symp 86–94

  20. Nicolaidis M (2007) GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies. IEEE Int Test Conf 4.3

  21. Nicolaidis M, Zorian Y (1998) On-line testing for VLSI – a compendium of approaches. J Electron Test Theory Appl 12(1–2):7–20

    Article  Google Scholar 

  22. Omana M, Rossi D, Bosio N, Metra C (2013) Low cost NBTI degradetion detection and masking approaches. IEEE Trans Comput 62(3):496–509

    Article  MathSciNet  Google Scholar 

  23. Omana M et al (2010) Self-checking monitor for NBTI due degradation. IEEE Int Mixed-Signals Sensors Syst Test Work 111–116

  24. Park SP, Roy K, Kang K (2009) Reliability implications of bias-temperature instability in digital ICs. IEEE Des Test Comput 23(6):8–17

    Article  Google Scholar 

  25. Samanta R, Venkataraman G, Shah N, Hu J (2008) Elastic timing scheme for energy-efficient and robust performance. Int Symp Qual Electron Des 537–542

  26. Valadimas S, Tsiatouhas Y, Arapoyanni A (2010) Timing error tolerance in nanometer ICs. IEEE Int On-Line Test Symp 283–288

  27. Valadimas S, Tsiatouhas Y, Arapoyanni A (2012) Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. IEEE Eur Test Symp 8–13

  28. Yu H, Nicolaidis M, Anghel L, Zergainoh N-E (2011) Efficient fault detection architecture design of latch-based low power DSP/MCU processor. IEEE European Test Symposium 177–183

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Authors and Affiliations

  1. Department of Informatics and Telecommunications, University of Athens, Athens, Greece

    Stefanos Valadimas, Angela Arapoyanni & Petros Xarchakos

  2. Department of Computer Science and Engineering, University of Ioannina, Ioannina, Greece

    Yiorgos Tsiatouhas

Authors
  1. Stefanos Valadimas
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  2. Yiorgos Tsiatouhas
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  3. Angela Arapoyanni
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  4. Petros Xarchakos
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Correspondence to Yiorgos Tsiatouhas.

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Responsible Editor: M. Violante

This research has been co-funded by the European Union (European Social Fund) and Greek national resources under the framework of the “Thales” project of the “Education & Lifelong Learning” Operational Program.

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Valadimas, S., Tsiatouhas, Y., Arapoyanni, A. et al. Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J Electron Test 29, 795–804 (2013). https://doi.org/10.1007/s10836-013-5419-3

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  • DOI: https://doi.org/10.1007/s10836-013-5419-3

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