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Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

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Abstract

This work extends to the switch level the verification and testing techniques based upon boolean satisfiability (SAT), so that SAT-based methodologies can be applied to circuits that cannot be well described at the gate level. The main achieved goal was to define a boolean model describing switch-level circuit operations as a SAT problem instance, to be applied to combinational equivalence checking and bridging-fault test generation. Results are provided for a set of combinational CMOS circuits, showing the feasibility of SAT-based verification and testing of switch-level circuits.

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Notes

  1. Hereafter, we will use the summation symbol to denote the logic disjunction and juxtaposition to denote the logic conjunction.

  2. We use lower case greek letters to denote the clausal formulas to be added to Φ.

References

  1. Acken J (1983) Testing for bridging faults (shorts) in CMOS Circuits. In: Proceedings of design automation conference, pp 717–718

  2. Arumi D, Rodriguez-Montanes R, Figueras J (2008) Experimental characterization of CMOS interconnect open defects. IEEE Trans Comput Aided Des Integr Circ Syst 27(1):123–136

    Article  Google Scholar 

  3. Barzilai Z, Beece D, Huisman L, Iyengar V, Silberman G (1986) SLS a fast switch level simulator for verification and fault coverage analysis. In: Proceedings of design automation conference, pp 164–170

  4. Blaauw D, et al (1987) Automatic generation of behavioral models from switch-level descriptions. In: Proceedings of design automation conference, pp 179–184

  5. Biere At, et al (eds) (2009) Handbook of satisfiability. IOS Press

  6. Brglez F (1985) A fast fault grader: analysis and applications. In: Proceedings of IEEE international test conference, pp 785–794

  7. Bryant R (1984) A switch-level model and simulator for MOS digital systems. IEEE Trans Comput 33:160–177

    Article  MATH  MathSciNet  Google Scholar 

  8. Bryant R (1987) A survey of switch-level algorithms. IEEE Des Test, 26–40

  9. Bryant R (1991) On the complexity of VLSI implementations and and graph repreentations of boolean functions with application to integer multiplication. IEEE Trans Comput 40:205–213

    Article  MATH  MathSciNet  Google Scholar 

  10. Bryant R, Schuster M (1985) Performance evaluation of FMOSSIM a concurrent switch-level fault simulator. In: Proceedings of design automation conference, pp 715719.

  11. Carrabina-Bordoll J, Ribas-Xirgo L (1995) Analysis of switch-level faults by symbolic simulation. In: Proceedings of design automation conference, pp 352–357

  12. Drechsler R, et al (2009) Test generation using boolean proof engines. Springer

  13. Drechsler R, et al (2008) On acceleration of SAT-based ATPG for industrial designs. IEEE Trans Comput-Aided Des Integr Circ Syst 27(7):1329–1333

    Article  Google Scholar 

  14. Een N, Sorensson N (2003) An estensible SAT solver. In: SAT

  15. Favalli M, Dalpasso M (2009) How many test vectors we need to detect a bridging fault? J Electron Test Theory Appl 25(1):79–95

    Article  Google Scholar 

  16. Hayes JP (1986) Pseudo boolean logic circuits. IEEE Trans Comput C-35:602–612

    Article  Google Scholar 

  17. Kuehlmann A, Ganai MK, Paruthi V (2001) Circuit-based boolean reasoning. In: Proceedings of design automation conference, pp 232–237

  18. Kundu S (1998) Gatemaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. In: Proceedings of international test conference, pp 372–381

  19. Larrabee T (1992) Test pattern generation using boolean satisfiability. IEEE Trans Comput-Aided Des Integr Circ Syst 11(1):4–15

    Article  Google Scholar 

  20. Lavo D, Larrabee T, Chess B (1996) Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis. In: Proceedings of IEEE international test conference, pp 611–619

  21. Lee K-J, Njinda C, Breuer M (1994) Switest: a switch level test generation system for CMOS combinational circuits. IEEE Trans Comput-Aided Des Integr Circ Syst 13(5):625–636

    Google Scholar 

  22. Lo C, Nham H, Bose A (1987) Algorithms for an advanced fault simulation system in MOTIS. IEEE Trans Comput-Aided Des Integr Circ Syst 6:232–240

    Google Scholar 

  23. Marques-Silva J, Glass T (1999) Combinational equivalence checking using satisfiability and recursive learning. In: Proceedings of design automation and test in Europe, pp 145–149

  24. Nayak D, Venkataraman S, Thadikaran P (2004) RAZOR: a tool for post-silicon scan ATPG pattern debug and its application. In: Proceedings of VLSI test symposium, pp 97–102

  25. Novakovsky S, Shyman S, Hanna Z (2002) High capacity and automatic functional extraction tool for industrial VLSI circuit designs. In: Proceedings of international computer aided design conference, pp 520–525

  26. Orshanky M, Nassif S, Boning D (2008) Design for manufacturability and statistical design: a constructive approach. Springer

  27. Ribas Xirgo L, Carrabina-Bordoll J (1999) Digital MOS circuit partitioning with symbolic modeling. In: Proceedings of design automation and test in Europe, pp 503–508

  28. Sentovich EM, et al (1992) SIS: a system for sequential circuit synthesis. Tech Rep, University of California, Berkeley

  29. Shih H, Abraham J (1985) Transistor-level test generation for physical failure in CMOS circuits. In: Proceedings of design automation conference, pp 825–828

  30. Singh KJ, Subrahmanyam PA (1995) Extracting RTL models from transistor netlists. In: Proceedings of international conference on computer-aided design, pp 11–17

  31. Weste N, Eshragian K (1993) Principles of VLSI design a system perspective. Addison-Wesley, Reading

    Google Scholar 

  32. Wiklund K, Magnusson T, Dahlgren P (2000) Switch-level test generation of competing bridging faults in the presence of feedback. Tech Rep, Department of Computer Engineering, Chalmers University of Technology, pp S-412

  33. Yang Y-S, et al (2006) Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(7):763–776

    Article  Google Scholar 

  34. Zhuang N, Wu H (1992) A new design of the CMOS full adder. IEEE J Solid State Circ 27(5):840–844

    Article  Google Scholar 

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Authors and Affiliations

  1. ENDIF - University of Ferrara, Viale Saragat, 1, 44122, Ferrara, Italy

    M. Favalli

  2. DEI - University of Padova, Via Gradenigo, 6/A, 35131, Padova, Italy

    M. Dalpasso

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  1. M. Favalli
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  2. M. Dalpasso
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Correspondence to M. Favalli.

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Responsible Editor: M. Hsiao

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Favalli, M., Dalpasso, M. Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits. J Electron Test 30, 41–55 (2014). https://doi.org/10.1007/s10836-014-5433-0

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