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An On-Chip Sensor to Monitor NBTI Effects in SRAMs

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Abstract

The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM’s robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs’ aging during the SoC’s lifetime based on the insertion of On-Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor’s capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor’s overheads is presented.

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References

  1. Ahmed F, Milor L (2010) Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. Proc. 28th IEEE VLSI Test Symposium, pp. 63–68

  2. Alam A (2008) Reliability- and process-variation aware design of integrated circuits. Microelectronics Reliability 48(8–9):1114–1122

    Article  Google Scholar 

  3. Boning D, Nassif S (2000) Models of Process Variations in Device and Interconnect, Design of High Performance Microprocessor Circuits, IEEE Press

  4. Borkar S (2005) Designing Reliable Systems from Unreliable Components: The challenges of transistor variability and degradation. IEEE Micro 25(6):10–16

    Article  Google Scholar 

  5. Calimera A, Macii E, Poncino M (2010) NBTI-Aware Clustered Power Gating, ACM Transactions on Design Automation of Electronic Systems, 16(1)

  6. Ceratti A, Copetti T, Bolzani Poehls L, Vargas F (2012) Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM. Proc. IEEE Latin-American Test Workshop, 2012

  7. Ferri C, Papagiannopoulou D, Iris Bahar R, Calimera A (2011) NBTI-aware data allocation strategies for scratchpad memory based embedded systems. Proc. 12th IEEE Latin American Test Workshop (LATW’11), March 27–30, Porto de Galinhas, Brazil

  8. Kang K, Alam M, Roy K (2007) Characterization of NBTI Induced temporal performance degradation in nano-scale SRAM array using IDDQ. Proc. International Test Conference, pp. 1–10

  9. Kang K, Kufluoglu H, Roy K, Ashraful Alam M (2007) Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans on Computer-Aided Design of Integratedd Circuits and Systems 26(10):1770–1781

    Article  Google Scholar 

  10. Keane J, Kim T-H, Kim CH (2010) An On-Chip NBTI Sensor for Mesauring pMOS Threshold Voltage Degradation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18:(6)

  11. Mahapatra S, Saha D, Varghese D, Kumar PB (2006) On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans Electron Dev 53(7):1583–1592

    Article  Google Scholar 

  12. PratesW, Bolzani L, Harutyunyan G, Davtyan A, Vargas F, Zorian Y (2013) Integrating embedded test infrastructure in SRAM cores to detect aging. Proc. IEEE International Online Test Symposium

  13. Qi Z, Wang J, Cabe A, Wooters S, Blalock T, Calhoun B, Stan M (2010) SRAM-based NBTI/PBTI sensor system design. Proc. Design Automation Conference, June 13–18, Anaheim, California, USA

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Acknowledgment

This work has been partially funded by CNPq (Science and Technology Foundation, Brazil) under contracts n. 301726/2008-6 and n. 556761/2009-0 and by FAPERGS/CAPES 014/2012.

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Authors and Affiliations

  1. Catholic University of Rio Grande do Sul – PUCRS, School of Engineering, Porto, Alegre, Brazil

    A. Ceratti, T. Copetti, L. Bolzani & F. Vargas

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  1. A. Ceratti
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  2. T. Copetti
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  3. L. Bolzani
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  4. F. Vargas
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  5. R. Fagundes
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Correspondence to L. Bolzani.

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Responsible Editor: V. Champac

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Ceratti, A., Copetti, T., Bolzani, L. et al. An On-Chip Sensor to Monitor NBTI Effects in SRAMs. J Electron Test 30, 159–169 (2014). https://doi.org/10.1007/s10836-014-5444-x

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  • DOI: https://doi.org/10.1007/s10836-014-5444-x

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