Abstract
Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. It investigates two secure Built-In Self-Test (BIST) solutions for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The schemes target high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The first scheme reuses existing FE blocks (for pattern generation and compression) to minimize the area overhead, while the second scheme tests all the FE blocks simultaneously to minimize the test time. The schemes are integrated in FE design and simulated; the results show that for the first test scheme, a SAF fault coverage of 95 % can be realized with no more than 47.1k clock cycles at the cost of a negligible area overhead of only 2.2 %; while for the second test scheme a SAF fault coverage of 95 % can be realized with 3.5k clock cycles at the cost of 18.6 % area overhead. Higher fault coverages are possible to realize at extra cost (i.e., either by extending the test time, or by adding extra hardware, or a combination of both).
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References
Agrawal D, Baktir S, Karakoyunlu D, Rohatgi P, Sunar B (2007) Trojan Detection using IC Fingerprinting, IEEE Symposium on Security and Privacy (SP) pp 296–310
Ali SS, Said SM, Sinanoglu O, Karri R (2013) Scan Attack in Presence of Mode-Reset Countermeasures. IEEE International online testing symposium (IOLTS) 230:231
Al-Yamani AA, McCluskey EJ (2003) Built-in reseeding for serial BIST. VLSI Test Symp:63–68
Bo Y, Kaijie W, Karri R (2004) Scan-based Side-Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard, Proceedings of International Test Conference, pp 339–344
Cortez M, Roelofs G, Hamdioui S, Di Natale G (2014) Testing PUF-Based Secure Key Storage Circuits Design, Automation and Test in Europe Conference and Exhibition (DATE) pp1–6
Da Rolt J, Di Natale G, Flottes ML, Rouzeyre B (2013) A Smart test controller for scan-chains in secure circuits. IEEE International On-line Testing Symposium (IOLTS):228–229
Da Rolt J, Di Natale G, Flottes ML, Rouzeyre B (2012) New security threats against chips containing scan chain structure. IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) p 110
Das A, Kocabaş U̇, Sadeghi AR, Verbauwhede I, Sadeghi AR, Verbauwhede I (2012) PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing Design, Automation and Test in Europe Conference and Exhibition pp 866–869
Di Natale G, Doulcier M, Flottes ML, Rouzeyre B (2010) Self-test techniques for crypto-devices. IEEE Trans VLSI Syst 18:2
Dodis Y, Reyzin L, Smith A (2004) Fuzzy Extractors: How to Generate Strong Keys from Biometrics and other Noisy Data, Advances in Cryptology-EUROCRYPT vol. 3027, LNCS, Springer Berlin Heidelberg, pp 523–540
Doulcier M, Flottes ML, Rouzeyre B (2008) AES-based BIST: self-test, test pattern generation and signature analysis. IEEE International Symposium on Electronic Design, Test & Applications, pp 314–321
Guajardo J, Kumar SS, Schrijen GJ, Tuyls P (2007) FPGA Intrinsic PUFs and Their Use for IP Protection. Workshop on Cryptographic Hardware and Embedded Systems (CHES):63–80
Hamdioui S, Di Natale G, van Battum G, Danger JL, Smailbegovic F, Tehranipoor M (2014) Hacking and Protecting IC Design, Automation and Test in Europe Conference and Exhibition, pp 1–7
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B (1995) Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Trans Comput 44(2):223–233
Hely D, Bancel F, Flottes ML, Rouzeyre B (2006) A secure Scan Design Methodology Design, Automation and Test in Europe Conference and Exhibition, pp 1–7
Krishna CV, Jas A, Touba NA (2001) Test vector encoding using partial LFSR reseeding. Int Test Conf:885–893
Lee J, Tehranipoor M, Patel C, Plusquellic J (2005) Securing scan design using lock and key technique. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) pp 51-62
Leest Vvd, Preneel B, Sluis Evd (2012) Soft Decision Error Correction for Compact Memory-Based PUFs using a Single Enrollment, Workshop on Cryptographic Hardware and Embedded Systems (CHES) pp 268–282
Linnartz JP, Tuyls P (2003) New shielding functions to enhance privacy and prevent misuse of biometric templates. In: Proceedings of Audio- and Video-Based Biometric Person Authentication AVBPA03, pp 393-402, Springer Berlin / Heidelberg
Lei L, Chakrabarty K (2004) Test set embedding for deterministic BIST using a reconfigurable interconnection network. IEEE Trans Comput Aided Des Integr Circ Syst 23(9):1289– 1305
Liu Y, Wu K, Karri R (2011) Scan-based attacks on linear feedback shift register based stream ciphers. ACM Trans Design Autom Electr Syst 16(2):20
Pless V (1986) Decoding the golay codes. IEEE Trans Inf Theory 32 (4):561–567
Skoric B, Tuyls P, Ophey W (2005) Robust key extraction from Physical Unclonable Functions, Applied Cryptography and Network Security, vol 3531 of LNCS, pp 99135, Springer Berlin / Heidelberg
Touba NA, McCluskey EJ (2001) Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans Comput Aided Des Integr Circ Syst 20(4):545–555
Wunderlich HJ, Kiefer G (1996) Bit-flipping BIST. IEEE/ACM Int Conf Comput Aided Des:337–343
Yang B, Wu K, Karri R (2006) Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans Comput Aided Des Integr Circ Syst 25(10):2287–2293
Acknowledgments
The authors would like to thank Geert-Jan Schrijen and Peter Simons from Intrinsic-ID B.V. for the useful discussions on the architecture of the Fuzzy Extractor used in this publication. It is worth noting that the work presented in this publication was partially sponsored by COST action TRUDEVICE IC1204.
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Cortez, M., Roelofs, G., Hamdioui, S. et al. Testing Methods for PUF-Based Secure Key Storage Circuits. J Electron Test 30, 581–594 (2014). https://doi.org/10.1007/s10836-014-5471-7
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DOI: https://doi.org/10.1007/s10836-014-5471-7