Skip to main content
SpringerLink
Log in

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21

Similar content being viewed by others

References

  1. Alexandrescu D, Anghel L, Nicolaidis M (2004) Simulating single event transients in VDSM ICs for ground level radiation. J Electron Test: Theory and Appl 20:413–421

    Article  Google Scholar 

  2. Baumann RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans on Device and Mater Reliab 5(3):305–316

    Article  MathSciNet  Google Scholar 

  3. Baumann RC (2005) “Single event effects in advanced CMOS Technology,” in Proc. IEEE Nuclear and Space Radiation Effects Conf. (NSREC) Short Course Text

  4. Buchner S, Baze M (2001) “Single-event transients in fast electronic circuits,” in Proc. IEEE Nuclear and Space Radiation Effects Conf. (NSREC) Short Course Text

  5. Chen L, Tahoori M (2012) “An efficient probability framework for error propagation and correlation estimation,” in Proc. IOLTS’12, pp. 170–175

  6. DasGupta S (2007) “Trends in single event pulse widths and pulse shapes in deep submicron CMOS,” M.S. Thesis. Vanderbilt University

  7. e2v releases the first space qualified GHz-class microprocessor, June 17, 2013. Http://http://www.e2v-us.com/news/e2v-releases-the-first-space-qualified-ghz-class-microprocessor/

  8. Entrena L, Valderas MG, Cardenal RF et al (2009) SET emulation considering electrical masking effects. IEEE Trans on Nucl Sci 56(4):2021–2025

    Article  Google Scholar 

  9. Fazeli M, Ahmadian SN, Miremadi SG et al. (2011) “Soft error rate estimation of digital circuits in the presence of multiple event transients (METs),” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1–6

  10. Gadlage MJ, Ahlbin JR, Bhuva BL et al (2011) Alpha-particle and focused-Ion-beam-induced single-event transient measurements in a bulk 65-nm CMOS technology. IEEE Trans on Nucl Sci 58(3):1093–1097

    Article  Google Scholar 

  11. George N, Lach J (2011) “Characterization of logic masking and error propagation in combinational circuits and effects on system vulnerability,” in Proc. IEEE/IFIP Dependable Systems & Networks, pp. 323–334

  12. Grosso M, Guzman-Miranda H, Aguirre MA (2013) Exploiting fault model correlations to accelerate SEU sensitivity assessment. IEEE Trans On Ind Inf 9(1):142–148

    Article  Google Scholar 

  13. Kehl N, Rosenstiel W (2011) An efficient SER estimation method for combinational circuits. IEEE Trans Reliab 60(4):742–747

    Article  Google Scholar 

  14. Kehl N, Rosentiel W (2011) An efficient SER estimation method for combinational circuits. IEEE Trans on Reliab 60(4):742–747

    Article  Google Scholar 

  15. Liu H, Cotter M, Datta S et al. (2014) “Soft Error Performance Evaluation on Emerging Low Power Devices”, IEEE Transactions on Device and Materials Reliability, no. 99

  16. Miskov-Zivanov N, Marculescu D (2010) Multiple transient faults in combinational and sequential circuits: a systematic approach. IEEE Trans on Comput-Aided Des of Integr Circ And Systems 29(10):1614–1627

    Article  Google Scholar 

  17. Narasimham B, Bhuva BL, Schrimpf RD et al (2007) Characterization of digital signal event transient pulse-widths in 130-nm and 90-nm CMOS technologies. IEEE Trans on Nucl Sci 54(6):2506–2510

    Article  Google Scholar 

  18. Pahlevanzadeh H, Yu Q (2014) “Systematic Analyses for Error Latching Probability of Single Event Transient”, in Proc. 15th International Symposium on Quality Electronic Design (ISQED), pp. 442–449

  19. Rao RR, Chopra K, Blaauw DT et al (2007) Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Trans on Comput-Aided Des of Integr Circ And Systems 26(3):468–479

    Article  Google Scholar 

  20. Satagopan M (1994) “Evaluation of single event vulnerability for complex digital circuits,” M.S. Thesis, Vanderbilt University

  21. Sayil S, Akkur AB, Gaspard N (2010) Single event crosstalk shielding for CMOS logic. Microelectron J 41:506–522

    Article  Google Scholar 

  22. Sun Y, Song C, Zhao Y et al. (2010) “FAST: A framework of accurate SER-estimation at transistor-level for logic circuits” in Proc. 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1707–1709

  23. Veeravalli VS, Steininger A, Schmid U (2014) “Measuring SET pulse widths in logic gates using digital infrastructure”, 15th international symposium on quality electronic design (ISQED), pp. 236–242

  24. Wrobel F, Dilillo L, Touboul AD et al. (2014) “Determining realistic parameters for the double exponential law that models transient current pulses”, IEEE Transactions on Nuclear Science, no. 99

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH, 03824, USA

    Hoda Pahlevanzadeh & Qiaoyan Yu

Authors
  1. Hoda Pahlevanzadeh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Qiaoyan Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Qiaoyan Yu.

Additional information

Responsible Editor: N. A. Touba

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Pahlevanzadeh, H., Yu, Q. A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients. J Electron Test 30, 595–609 (2014). https://doi.org/10.1007/s10836-014-5476-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-014-5476-2

Keywords

Search

Navigation