Skip to main content
SpringerLink
Log in

Improving Semiconductor Reliability with Advanced Engineering Methods in Test Program Development

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Advancing semiconductor technology in combination with new assembly and packaging technologies are unfolding a new level of challenges for production testing. Reliability of semiconductors should be ensured by applying dedicated techniques within production testing addressing various aging aspects such as: device wear-out related degradation or reduced operational voltage headroom. Thus, test program quality is emerging as a major concern, as it is directly translating into microelectronics reliability and devices quality. With the heightened sensitivity of semiconductor technology to smallest deviations in test methods from the allowed operational range, the risk of accidentally degrading the integrated circuits reliability increases significant. In this paper we propose an approach that addresses the demand for improving semiconductor technology reliability production tests quality. The presented industry usage based case studies, in combination with described techniques, provide a set of valuable practical guidelines.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. Chen X, Wang Y, Cao Y, Ma Y, Yang H (2012) Variation-aware supply voltage assignment for simultaneous power and aging optimization. IEEE Trans Very Large Scale Integration (VLSI) Syst 20(11):2143–2147

    Article  Google Scholar 

  2. Han S, Kim B-S, Kim J (2013) Variation-aware aging analysis in digital ICs. IEEE Trans Very Large Scale Integration (VLSI) Syst 21(12):2214–2225

    Article  Google Scholar 

  3. Infineon Technologies AG (2014) Company home webpage, viewed June 2014, <http://www.infineon.com/cms/en/product/index.html>

  4. ITRS (2013) International Technology Roadmap for Semiconductors 2013 Edition, viewed June 2014, <http://public.itrs.net/>

  5. Jeng S-L, Huang B-Y, Meeker WQ (2011) Accelerated destructive degradation tests robust to distribution misspecification. IEEE Trans Reliab 60(4):701–711

    Article  Google Scholar 

  6. Journal of Electronic Testing (2012) Special Issue on Testing of Three-Dimensional Stacked Integrated Circuits, 28(1)

  7. Meeker WQ (2010) Trends in the Statistical Assessment of Reliability, in Advances in Degradation Modeling, Statistics for Industry and Technology. In: Nikulin MS et al (ed) Springer

  8. Nahar A, Butler KM, Carulli JM, Weinberger, C (2009) Quality improvement and cost reduction using statistical outlier methods, Proc. IEEE International Conference on Computer Design, pp. 64–69

  9. Nourivand A, Al-Khalili AJ, Savaria Y (2012) Postsilicon tuning of standby supply voltage in SRAMs to reduce yield losses Due to parametric data-retention failures. IEEE Trans Very Large Scale Integration (VLSI) Syst 20(1):29–41

    Article  Google Scholar 

  10. Suhir E (2013) Could electronics reliability be predicted, quantified and assured? Microelectron Reliab 53(7):925–936, ISSN 0026–2714

    Article  Google Scholar 

  11. Vock S, Escalona O, Turner C, Owens F (2012) Challenges for semiconductor test engineering: a review paper. J Electron Test Theory Appl 28(3):365–374

    Article  Google Scholar 

  12. Vock S, Escalona O, Turner C, Owens F (2014) The Use of software engineering methods for efficacious test program creation: a supportive evidence based case study. J Electron Test Theory Appl. doi:10.1007/s10836-014-5462-8

    MATH  Google Scholar 

  13. Vock S, Escalona OJ, Owens FJ (2010) Commercial Challenges and Quality Robustness Issue in Semiconductor Manufacture Test and Measurement, Proc. 27th International Manufacturing Conference, Galway Institute of Technology, < http://eprints.ulster.ac.uk>

Download references

Author information

Authors and Affiliations

  1. Faculty of Computing and Engineering, University of Ulster, Shore Road, Newtownabbey, Co., Antrim, BT37 0QB, UK

    Stefan Vock

  2. Infineon Technologies AG, Am Campeon 1-12, 85579, Neubiberg, Germany

    Stefan Vock

  3. Engineering Research Institute, School of Engineering, University of Ulster, Shore Road, Newtownabbey, Co. Antrim, BT37 0QB, UK

    Omar Escalona & Colin Turner

Authors
  1. Stefan Vock
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Omar Escalona
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Colin Turner
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Stefan Vock.

Additional information

Responsible Editor: K. Chakrabarty.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Vock, S., Escalona, O. & Turner, C. Improving Semiconductor Reliability with Advanced Engineering Methods in Test Program Development. J Electron Test 31, 107–117 (2015). https://doi.org/10.1007/s10836-014-5495-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-014-5495-z

Keywords

Search

Navigation